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| author | Wim Vervoorn <wvervoorn@eltan.com> | 2019-12-16 14:21:09 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-20 17:50:28 +0000 |
| commit | 67117c3971f16e4b47e927821a19f110b4885111 (patch) | |
| tree | 321d4462a87aaeed64b8926df22a5cf0085c80c5 /src/soc/intel/braswell/chip.c | |
| parent | 0e45b2875add588ddada7f40e294db99d62c3c3c (diff) | |
| download | coreboot-67117c3971f16e4b47e927821a19f110b4885111.tar.gz coreboot-67117c3971f16e4b47e927821a19f110b4885111.tar.bz2 coreboot-67117c3971f16e4b47e927821a19f110b4885111.zip | |
{drivers,soc}/intel/fsp1_1: Move chipset specific logo handling to SoC
FSP logo handling used PcdLogoPtr and PcdLogoSize which are elements of
the chipset specific FSP structures.
Create soc_load_logo() which will pass the logo pointer and size.
This function will call fsp_load_logo which will load the logo.
BUG=NA
TEST= Build and verified logo is displayed on Facebook FBG1701
Change-Id: I86943e64ca1ddd05e7e88fc6b882cfd33b98272e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37791
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell/chip.c')
| -rw-r--r-- | src/soc/intel/braswell/chip.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index d179cead2536..026b28188124 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -181,6 +181,11 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) board_silicon_USB2_override(params); } +const struct cbmem_entry *soc_load_logo(SILICON_INIT_UPD *params) +{ + return fsp_load_logo(¶ms->PcdLogoPtr, ¶ms->PcdLogoSize); +} + void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new) { |