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| author | shkim <sh_.kim@samsung.com> | 2015-09-22 17:53:58 +0900 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-28 20:46:23 +0100 |
| commit | cc728f02846a1752215503dc7897caf6fc5a1fc1 (patch) | |
| tree | 807c58c07a79e8e0d98777dc72e27f78efac92f1 /src/soc/intel/braswell/include | |
| parent | e8cc52fab012798dd9f5ad12cd6a8d238ea360c7 (diff) | |
| download | coreboot-cc728f02846a1752215503dc7897caf6fc5a1fc1.tar.gz coreboot-cc728f02846a1752215503dc7897caf6fc5a1fc1.tar.bz2 coreboot-cc728f02846a1752215503dc7897caf6fc5a1fc1.zip | |
soc/braswell: Add interface to program USB2_COMPBG register
Add interface to program USB2_COMPBG register to set
HS_DISC_BG and HS_SQ reference voltage for each project.
TEST=Get build success and do EFT test
Original-Reviewed-on: https://chromium-review.googlesource.com/300846
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Tested-by: shkim <sh_.kim@samsung.com>
Change-Id: If2201829e1a16b4f9916547f08c24e9291358325
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Signed-off-by: shkim <sh_.kim@samsung.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12739
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/braswell/include')
| -rw-r--r-- | src/soc/intel/braswell/include/soc/iosf.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h index add602f47b85..5afca3e123b6 100644 --- a/src/soc/intel/braswell/include/soc/iosf.h +++ b/src/soc/intel/braswell/include/soc/iosf.h @@ -69,6 +69,8 @@ uint32_t iosf_port58_read(int reg); void iosf_port58_write(int reg, uint32_t val); uint32_t iosf_scc_read(int reg); void iosf_scc_write(int reg, uint32_t val); +uint32_t iosf_usbphy_read(int reg); +void iosf_usbphy_write(int reg, uint32_t val); #if ENV_RAMSTAGE uint64_t reg_script_read_iosf(struct reg_script_context *ctx); @@ -91,6 +93,7 @@ void reg_script_write_iosf(struct reg_script_context *ctx); #define IOSF_PORT_0x5a 0x5a #define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */ #define IOSF_PORT_SCC 0x63 /* Storage Control Cluster */ +#define IOSF_PORT_USBPHY 0x43 /* USB PHY */ #define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ #define IOSF_PORT_0xa2 0xa2 #define IOSF_PORT_SSUS 0xa8 /* SUS */ @@ -109,6 +112,8 @@ void reg_script_write_iosf(struct reg_script_context *ctx); #define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1) #define IOSF_OP_READ_SCC 0x06 #define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1) +#define IOSF_OP_READ_USBPHY 0x06 +#define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1) /* * BUNIT Registers. @@ -176,6 +181,11 @@ void reg_script_write_iosf(struct reg_script_context *ctx); # define LPE_PCICFGCTR1_ACPI_INT_EN (1 << 1) /* + * USBPHY Registers + */ +#define USBPHY_COMPBG 0x7f04 + +/* * IO Sideband Function */ |