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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-14 05:41:41 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-15 06:55:59 +0000 |
| commit | faf20d30a6e451d45e29613e3f4603dc72771843 (patch) | |
| tree | d1c3df6e87473d66633fb3a4a8cec736fdda2cd7 /src/soc/intel/braswell/smm.c | |
| parent | f091f4daf7e76cff3cdf9b7a19bb77281fb6af9d (diff) | |
| download | coreboot-faf20d30a6e451d45e29613e3f4603dc72771843.tar.gz coreboot-faf20d30a6e451d45e29613e3f4603dc72771843.tar.bz2 coreboot-faf20d30a6e451d45e29613e3f4603dc72771843.zip | |
soc/intel: Rename some SMM support functions
Rename southbridge_smm_X to smm_southbridge_X.
Rename most southcluster_smm_X to smm_southbridge_X.
Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell/smm.c')
| -rw-r--r-- | src/soc/intel/braswell/smm.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c index fe681c9d909a..364cda5b5af2 100644 --- a/src/soc/intel/braswell/smm.c +++ b/src/soc/intel/braswell/smm.c @@ -19,6 +19,7 @@ #include <device/mmio.h> #include <console/console.h> #include <cpu/x86/smm.h> +#include <cpu/intel/smm_reloc.h> #include <device/device.h> #include <device/pci.h> #include <soc/iomap.h> @@ -28,12 +29,12 @@ /* Save settings which will be committed in SMI functions. */ static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT]; -void southcluster_smm_save_param(int param, uint32_t data) +void smm_southcluster_save_param(int param, uint32_t data) { smm_save_params[param] = data; } -void southcluster_smm_clear_state(void) +void smm_southbridge_clear_state(void) { uint32_t smi_en; @@ -58,7 +59,7 @@ void southcluster_smm_clear_state(void) clear_pmc_status(); } -static void southcluster_smm_route_gpios(void) +static void smm_southcluster_route_gpios(void) { void *gpio_rout = (void *)(PMC_BASE_ADDRESS + GPIO_ROUT); const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI; @@ -82,7 +83,7 @@ static void southcluster_smm_route_gpios(void) outl(alt_gpio_reg, alt_gpio_smi); } -void southcluster_smm_enable_smi(void) +void smm_southbridge_enable_smi(void) { uint16_t pm1_events = PWRBTN_EN | GBL_EN; @@ -93,7 +94,7 @@ void southcluster_smm_enable_smi(void) disable_gpe(PME_B0_EN); /* Set up the GPIO route. */ - southcluster_smm_route_gpios(); + smm_southcluster_route_gpios(); /* * Enable SMI generation: |