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| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-12 17:13:05 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-15 11:22:28 +0000 |
| commit | 06e6983002ccf2af41e2739c21d0b9e79608d8c9 (patch) | |
| tree | 07ea58b4be3c31033b6a4dc64c632dd5ea6b506c /src/soc/intel/braswell | |
| parent | 77a7520385242bd2c9e323ecc74490b383c22f5e (diff) | |
| download | coreboot-06e6983002ccf2af41e2739c21d0b9e79608d8c9.tar.gz coreboot-06e6983002ccf2af41e2739c21d0b9e79608d8c9.tar.bz2 coreboot-06e6983002ccf2af41e2739c21d0b9e79608d8c9.zip | |
soc/intel/braswell: Prevent NULL pointer dereference
Exit early if the chipset power state info isn't in CBMEM. Return -1 in
order to ensure the one caller of this function exits early as well.
Found-by: Coverity CID 1442304
Change-Id: Ifa42ba3024d3144de486d90ed7752820482549bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49359
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell')
| -rw-r--r-- | src/soc/intel/braswell/ramstage.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 7b92c52e78a2..de90cb7b610a 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -125,6 +125,9 @@ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); static uint32_t gpe0_sts; + if (!ps) + return -1; + *pm1 = ps->pm1_sts & ps->pm1_en; gpe0_sts = ps->gpe0_sts & ps->gpe0_en; |