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| author | Angel Pons <th3fanbus@gmail.com> | 2021-04-19 22:31:49 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-06-14 09:59:40 +0000 |
| commit | 68d8357dab55660058ad1ab8dca34fd03e0adbb5 (patch) | |
| tree | 2dc32faf914baa992e67d8af7f7868422c16a046 /src/soc/intel/broadwell/acpi/device_nvs.asl | |
| parent | 07baa7a7f06369d9dc795c5a9b34314e88d14dd8 (diff) | |
| download | coreboot-68d8357dab55660058ad1ab8dca34fd03e0adbb5.tar.gz coreboot-68d8357dab55660058ad1ab8dca34fd03e0adbb5.tar.bz2 coreboot-68d8357dab55660058ad1ab8dca34fd03e0adbb5.zip | |
soc/intel/broadwell/pch: Replace ACPI device NVS
The same functionality can be provided through a runtime-generated SSDT.
The remaining parts of device NVS are removed in a follow-up.
Since the SSDTs are only loaded after the DSDT (if loaded at all), using
SSDT-provided objects outside method bodies is not possible: the objects
are not yet in OSPM's ACPI namespace, which causes in ACPI errors. Owing
to this, the operation regions used by the _PS0 and _PS3 methods need to
be moved into the SSDT, as they depend on the SSDT-provided BAR1 values.
Tested on out-of-tree Compal LA-A992P, generated SSDT disassembles with
no errors and contains expected values. Linux does not complain either.
Change-Id: I89fb658fbb10a8769ebea2e6535c45cd7c212d06
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/broadwell/acpi/device_nvs.asl')
| -rw-r--r-- | src/soc/intel/broadwell/acpi/device_nvs.asl | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/src/soc/intel/broadwell/acpi/device_nvs.asl b/src/soc/intel/broadwell/acpi/device_nvs.asl deleted file mode 100644 index fb95df8e6e17..000000000000 --- a/src/soc/intel/broadwell/acpi/device_nvs.asl +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Field (DNVS, ByteAcc, NoLock, Preserve) -{ - /* Device enables in ACPI mode */ - - S0EN, 8, // DMA Enable - S1EN, 8, // I2C0 Enable - S2EN, 8, // I2C1 Enable - S3EN, 8, // SPI0 Enable - S4EN, 8, // SPI1 Enable - S5EN, 8, // UART0 Enable - S6EN, 8, // UART1 Enable - S7EN, 8, // SDIO Enable - S8EN, 8, // ADSP Enable - - /* BAR 0 */ - - S0B0, 32, // DMA BAR0 - S1B0, 32, // I2C0 BAR0 - S2B0, 32, // I2C1 BAR0 - S3B0, 32, // SPI0 BAR0 - S4B0, 32, // SPI1 BAR0 - S5B0, 32, // UART0 BAR0 - S6B0, 32, // UART1 BAR0 - S7B0, 32, // SDIO BAR0 - S8B0, 32, // ADSP BAR0 - - /* BAR 1 */ - - S0B1, 32, // DMA BAR1 - S1B1, 32, // I2C0 BAR1 - S2B1, 32, // I2C1 BAR1 - S3B1, 32, // SPI0 BAR1 - S4B1, 32, // SPI1 BAR1 - S5B1, 32, // UART0 BAR1 - S6B1, 32, // UART1 BAR1 - S7B1, 32, // SDIO BAR1 - S8B1, 32, // ADSP BAR1 -} |