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| author | Aaron Durbin <adurbin@chromium.org> | 2017-09-15 11:51:58 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-20 23:53:44 +0000 |
| commit | b9d9b79cedebcbcd46bd457ab2f70239a22ab572 (patch) | |
| tree | 45834f05b24e276943e63f62ced6c4aaf60edfa7 /src/soc/intel/broadwell/include/soc/pm.h | |
| parent | 3118b6277d743100a4a0718edbfea02ddb50f625 (diff) | |
| download | coreboot-b9d9b79cedebcbcd46bd457ab2f70239a22ab572.tar.gz coreboot-b9d9b79cedebcbcd46bd457ab2f70239a22ab572.tar.bz2 coreboot-b9d9b79cedebcbcd46bd457ab2f70239a22ab572.zip | |
soc/intel/broadwell: refactor rtc failure checking
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred.
BUG=b:63054105
Change-Id: Ia0a38f00d2a5c7270e24bdd35ecab7fbba1016d4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/include/soc/pm.h')
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/pm.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/soc/intel/broadwell/include/soc/pm.h index 18004fa77dae..343cf2ba688e 100644 --- a/src/soc/intel/broadwell/include/soc/pm.h +++ b/src/soc/intel/broadwell/include/soc/pm.h @@ -155,4 +155,7 @@ void disable_gpe(uint32_t mask); /* Return the selected ACPI SCI IRQ */ int acpi_sci_irq(void); +/* Return non-zero when RTC failure happened. */ +int rtc_failure(void); + #endif |