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| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-23 12:40:07 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-10 07:27:57 +0000 |
| commit | f21e5c06cd7d731857ffb2483ce6f39ef0afa1b1 (patch) | |
| tree | b092d62bf96277ec96839856ea86a9ad343f29ea /src/soc/intel/broadwell/include/soc/pm.h | |
| parent | e0f058ffa8309bd902802074418b5c6e0075a8aa (diff) | |
| download | coreboot-f21e5c06cd7d731857ffb2483ce6f39ef0afa1b1.tar.gz coreboot-f21e5c06cd7d731857ffb2483ce6f39ef0afa1b1.tar.bz2 coreboot-f21e5c06cd7d731857ffb2483ce6f39ef0afa1b1.zip | |
soc/intel/broadwell/pch: Drop `acpi_sci_irq` function
The SCI IRQ is always set to IRQ 9 in the bootblock. To allow using
common MADT code on Broadwell, hardcode it as 9 everywhere.
Change-Id: I84345b7985b1996369cecc4bcb0a3668d002a922
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/broadwell/include/soc/pm.h')
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/pm.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/soc/intel/broadwell/include/soc/pm.h index 352394cb21a8..40467ed1dd31 100644 --- a/src/soc/intel/broadwell/include/soc/pm.h +++ b/src/soc/intel/broadwell/include/soc/pm.h @@ -139,9 +139,6 @@ void disable_all_gpe(void); void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); -/* Return the selected ACPI SCI IRQ */ -int acpi_sci_irq(void); - /* STM Support */ uint16_t get_pmbase(void); |