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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-05-12 13:44:22 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-05-14 23:22:02 +0000 |
| commit | cadc70f7974db25144381b3ea26d4b660233f4dd (patch) | |
| tree | de9e0677c328fe3d90389298c00f8831d0a6984d /src/soc/intel/broadwell/romstage/romstage.c | |
| parent | 57459dbeacb4759c3352206464b6c19b7add00d5 (diff) | |
| download | coreboot-cadc70f7974db25144381b3ea26d4b660233f4dd.tar.gz coreboot-cadc70f7974db25144381b3ea26d4b660233f4dd.tar.bz2 coreboot-cadc70f7974db25144381b3ea26d4b660233f4dd.zip | |
soc/intel/broadwell: Move GPIO init to a common place
This also links the gpio configuration instead of including it as a
header.
Change-Id: I9309d2b842495f6cff33fdab18aa139a82c1959c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/soc/intel/broadwell/romstage/romstage.c')
| -rw-r--r-- | src/soc/intel/broadwell/romstage/romstage.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 2531665f1fb5..7847829ac6e8 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -27,6 +27,7 @@ #include <romstage_handoff.h> #include <stage_cache.h> #include <timestamp.h> +#include <soc/gpio.h> #include <soc/me.h> #include <soc/pei_data.h> #include <soc/pm.h> @@ -100,6 +101,9 @@ static void romstage_main(uint64_t tsc, uint32_t bist) /* Set CPU frequency to maximum */ set_max_freq(); + /* Initialize GPIOs */ + init_gpios(mainboard_gpio_config); + /* Call into mainboard. */ mainboard_romstage_entry(&rp); |