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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-19 18:39:22 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-28 10:08:23 +0000 |
| commit | e8a3af10691a4831a85d8760f7fcb20f78065f78 (patch) | |
| tree | dff1c9bbfdee73e0283223c334b168ab4b0c4662 /src/soc/intel/broadwell | |
| parent | 560c3f5ccfff0fc289bb46f1b1b6c4236817590a (diff) | |
| download | coreboot-e8a3af10691a4831a85d8760f7fcb20f78065f78.tar.gz coreboot-e8a3af10691a4831a85d8760f7fcb20f78065f78.tar.bz2 coreboot-e8a3af10691a4831a85d8760f7fcb20f78065f78.zip | |
sb,soc/intel: Apply transitional flag TCO_SPACE_NOT_YET_SPLIT
Tree is inconsistent with the use of TCO register space offsets and
related preprocessor defines. The legacy space was offset from ACPI
PM base by 0x60, but this changed with later platforms. The convenient
way is to define the TCO registers relative to its base address and
subtract 0x60 here, but this change cannot be easily done tree-wide or
in one go.
For the transient period, apply TCO_SPACE_NOT_YET_SPLIT flag until
all platforms use a clean style of tco_{read,write} accessor functions
instead of {read,write}_pmbase16(), or worse, inw/outl().
Change-Id: I16213cdb13f98fccb261004b31e81a9a44cb6e3b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/broadwell')
| -rw-r--r-- | src/soc/intel/broadwell/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/pm.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/pch/Kconfig | 1 |
3 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 5b73f4f941de..3878f142a7c3 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -12,6 +12,7 @@ config SOC_SPECIFIC_OPTIONS select INTEL_GMA_ACPI select MRC_SETTINGS_PROTECT select REG_SCRIPT + select TCO_SPACE_NOT_YET_SPLIT config BROADWELL_LPDDR3 bool diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/soc/intel/broadwell/include/soc/pm.h index 52fd36443020..8bbc2de47292 100644 --- a/src/soc/intel/broadwell/include/soc/pm.h +++ b/src/soc/intel/broadwell/include/soc/pm.h @@ -53,12 +53,15 @@ #define SWGPE_CTRL (1 << 1) #define DEVACT_STS 0x44 #define PM2_CNT 0x50 + +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO1_CNT 0x60 #define TCO_TMR_HLT (1 << 11) #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 #define TCO2_STS_SECOND_TO (1 << 1) +#endif #define GPE0_REG_MAX 4 #define GPE0_REG_SIZE 32 diff --git a/src/soc/intel/broadwell/pch/Kconfig b/src/soc/intel/broadwell/pch/Kconfig index 4e187ff1145c..4800f3f804b4 100644 --- a/src/soc/intel/broadwell/pch/Kconfig +++ b/src/soc/intel/broadwell/pch/Kconfig @@ -23,6 +23,7 @@ config PCH_SPECIFIC_OPTIONS select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SPI_FLASH + select TCO_SPACE_NOT_YET_SPLIT config EHCI_BAR hex |