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| author | Pratik Prajapati <pratikkumar.v.prajapati@intel.com> | 2017-08-16 11:42:40 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-17 19:23:48 +0000 |
| commit | 201fa8ffe5908b7fe004fa6a72ccebbde38acb9b (patch) | |
| tree | 2e4d5cb3db2c30bceece315e55f07449e95fc385 /src/soc/intel/cannonlake/chip.c | |
| parent | dc1e6bc2774e0fad2eec31d281c4e3ed22c16fe7 (diff) | |
| download | coreboot-201fa8ffe5908b7fe004fa6a72ccebbde38acb9b.tar.gz coreboot-201fa8ffe5908b7fe004fa6a72ccebbde38acb9b.tar.bz2 coreboot-201fa8ffe5908b7fe004fa6a72ccebbde38acb9b.zip | |
intel/cannonlake/chip: Add initial PCI enum support
Add callbacks for initial PCI devices enumeration.
Change-Id: Ia8a51973aa2b805d62590114bfc49968244b1668
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.c')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.c | 31 |
1 files changed, 30 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 2f893e3d4896..62181a383f3a 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -15,9 +15,9 @@ #include <chip.h> #include <console/console.h> +#include <device/device.h> #include <device/pci.h> #include <fsp/api.h> -#include <fsp/api.h> #include <fsp/util.h> #include <romstage_handoff.h> #include <soc/ramstage.h> @@ -29,8 +29,37 @@ void soc_init_pre_device(void *chip_info) fsp_silicon_init(romstage_handoff_is_resume()); } +static void pci_domain_set_resources(device_t dev) +{ + assign_resources(dev->link_list); +} + +static struct device_operations pci_domain_ops = { + .read_resources = &pci_domain_read_resources, + .set_resources = &pci_domain_set_resources, + .scan_bus = &pci_domain_scan_bus, + .ops_pci_bus = &pci_bus_default_ops, +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = DEVICE_NOOP, +}; + +static void soc_enable(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) + dev->ops = &pci_domain_ops; + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) + dev->ops = &cpu_bus_ops; +} + struct chip_operations soc_intel_cannonlake_ops = { CHIP_NAME("Intel Cannonlake") + .enable_dev = &soc_enable, .init = &soc_init_pre_device, }; |