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| author | Subrata Banik <subrata.banik@intel.com> | 2019-01-29 11:04:25 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-02-07 04:50:37 +0000 |
| commit | 6527b1acc7a020e1f0594a7ea30daed0978dd5fd (patch) | |
| tree | a0d3dddb1fe8fd5df5f8be2f5eee97cb887f89d1 /src/soc/intel/cannonlake/chip.c | |
| parent | 12431d6eef53454907711dcd1545a0540ba57bbe (diff) | |
| download | coreboot-6527b1acc7a020e1f0594a7ea30daed0978dd5fd.tar.gz coreboot-6527b1acc7a020e1f0594a7ea30daed0978dd5fd.tar.bz2 coreboot-6527b1acc7a020e1f0594a7ea30daed0978dd5fd.zip | |
soc/intel/cannonlake: Add Whiskeylake SoC kconfig
This patch performs below tasks
1. Create SOC_INTEL_COMMON_CANNONLAKE_BASE kconfig.
2. Allow required SoC to select this kconfig to extend CANNONLAKE
SoC support and add incremental changes.
3. Select correct SoC support for hatch, sarien, cflrvps
and whlrvp.
* Hatch is WHL SoC based board
* Sarien is WHL SoC based board
* CFLRVP U/8/11 are CFL SoC based board
* WHLRVP is based on WHL SoC
4. Add correct FSP blobs path for WHL SoC based designs.
Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.c')
0 files changed, 0 insertions, 0 deletions