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| author | Eugene Myers <edmyers@tycho.nsa.gov> | 2021-06-16 07:55:58 -0400 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2023-06-10 03:19:55 +0000 |
| commit | 60004e276ab0a5845f0652c7d8dd40ed7c5ab1b9 (patch) | |
| tree | 2d219b293c8bf55faf409fe25966873911481011 /src/soc/intel/cannonlake | |
| parent | 6ffb50080a2978cbffe952bee4b6c6b7877c4224 (diff) | |
| download | coreboot-60004e276ab0a5845f0652c7d8dd40ed7c5ab1b9.tar.gz coreboot-60004e276ab0a5845f0652c7d8dd40ed7c5ab1b9.tar.bz2 coreboot-60004e276ab0a5845f0652c7d8dd40ed7c5ab1b9.zip | |
soc/intel: Add get_pmbase
Originally a part of security/intel/stm.
Add get_pmbase to the intel platform setup code.
get_pmbase is used by the coreboot STM setup functions to ensure
that the pmbase is accessable by the SMI handler during runtime.
The pmbase has to be accounted for in the BIOS resource list so
that the SMI handler is allowed this access.
Original-Change-Id: If6f6295c5eba9eb20e57ab56e7f965c8879e93d2
Original-Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/37990
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change-Id: I7f9ef32946a17aa0bbcbc375bc34b48e62620694
Signed-off-by: Eugene Myers <edmyers@tycho.nsa.gov>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/pm.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/pmutil.c | 6 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index 5b85e74bf5ec..356f0bcc6fcc 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -172,5 +172,8 @@ void pmc_set_disb(void); /* Clear PMCON status bits */ void pmc_clear_pmcon_sts(void); +/* STM Support */ +uint16_t get_pmbase(void); + #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 428a89fe4b3d..577487318030 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -273,3 +273,9 @@ void soc_fill_power_state(struct chipset_power_state *ps) printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +} |