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| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-02-20 14:37:03 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-02-22 09:59:03 +0000 |
| commit | 51605e2c9e21d0aa81a8368ef818b48cd34f3bfd (patch) | |
| tree | a3abdc28422e0bd32293be5b8793146c8c28fe38 /src/soc/intel/cannonlake | |
| parent | 9672b540874bf3a27df0b35ae94ada32e5a8c601 (diff) | |
| download | coreboot-51605e2c9e21d0aa81a8368ef818b48cd34f3bfd.tar.gz coreboot-51605e2c9e21d0aa81a8368ef818b48cd34f3bfd.tar.bz2 coreboot-51605e2c9e21d0aa81a8368ef818b48cd34f3bfd.zip | |
soc/intel/cannonlake: Clear EMMC timeout register
Clear EMMC timeout register to avoid EMMC issue according to cannonlake
bios writer guide.
BUG=b.71586766
TEST=Install OS into EMMC successfully on meowth P1 platform.
Change-Id: I39e927a2c312c94561213f9f7c3319dcafa426b9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/scs.asl | 10 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/southbridge.asl | 6 |
2 files changed, 13 insertions, 3 deletions
diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 4d68d563911a..4062e704a1e6 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <soc/pcr_ids.h> + Scope (\_SB.PCI0) { /* EMMC */ Device(PEMC) { @@ -34,6 +36,10 @@ Scope (\_SB.PCI0) { Store(0, PGEN) // Disable PG + /* Clear register 0x1C20/0x4820 */ + ^^PCRA (PID_EMMC, 0x1C20, 0x0) + ^^PCRA (PID_EMMC, 0x4820, 0x0) + /* Set Power State to D0 */ And (PMCR, 0xFFFC, PMCR) Store (PMCR, ^TEMP) @@ -78,6 +84,10 @@ Scope (\_SB.PCI0) { { Store (0, PGEN) /* Disable PG */ + /* Clear register 0x1C20/0x4820 */ + ^^PCRA (PID_SDX, 0x1C20, 0x0) + ^^PCRA (PID_SDX, 0x4820, 0x0) + /* Set Power State to D0 */ And (PMCR, 0xFFFC, PMCR) Store (PMCR, ^TEMP) diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 8d74da9f426c..4a62485324c1 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -19,12 +19,12 @@ /* PCI IRQ assignment */ #include "pci_irqs.asl" -/* eMMC, SD Card */ -#include "scs.asl" - /* PCR access */ #include <soc/intel/common/acpi/pcr.asl> +/* eMMC, SD Card */ +#include "scs.asl" + /* GPIO controller */ #include "gpio.asl" |