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authorSubrata Banik <subratabanik@google.com>2022-04-18 11:46:39 +0530
committerFelix Held <felix-coreboot@felixheld.de>2022-04-21 13:06:51 +0000
commit5685cbb9587bc74bb46a8240bd0f99e1e54ef7cd (patch)
treec4d032b449b0c944d02f89bab26d13843cf7a08e /src/soc/intel/cannonlake
parent86f4352a47a15fe69a0ea2b3a2a455ef863e7917 (diff)
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soc/intel/cannonlake: Drop unused LPC BIOS Control macro
This patch drops unused LPC BIOS control macros. BUG=b:211954778 TEST=Able to build and boot google/hatch. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib309c6bd0f27115357f8e62200808764748f51a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r--src/soc/intel/cannonlake/include/soc/lpc.h4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/lpc.h b/src/soc/intel/cannonlake/include/soc/lpc.h
index a510bc51a933..c16b732b2691 100644
--- a/src/soc/intel/cannonlake/include/soc/lpc.h
+++ b/src/soc/intel/cannonlake/include/soc/lpc.h
@@ -24,10 +24,6 @@
#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
#define LGMR 0x98 /* LPC Generic Memory Range */
-#define BIOS_CNTL 0xdc
-#define LPC_BC_BILD (1 << 7) /* BILD */
-#define LPC_BC_LE (1 << 1) /* LE */
-#define LPC_BC_EISS (1 << 5) /* EISS */
#define PCCTL 0xE0 /* PCI Clock Control */
#define CLKRUN_EN (1 << 0)