summaryrefslogtreecommitdiffstats
path: root/src/soc/intel/cannonlake
diff options
context:
space:
mode:
authorFelix Singer <felixsinger@posteo.net>2022-01-02 01:09:03 +0100
committerFelix Singer <felixsinger@posteo.net>2022-06-09 08:58:57 +0000
commit5c9560407931963fd64418b48e7da26e5e4051dc (patch)
tree907675942584e30cd0b440082988cee75b3e3c15 /src/soc/intel/cannonlake
parent1225083591b9f125314ab959125d027fb07e8e63 (diff)
downloadcoreboot-5c9560407931963fd64418b48e7da26e5e4051dc.tar.gz
coreboot-5c9560407931963fd64418b48e7da26e5e4051dc.tar.bz2
coreboot-5c9560407931963fd64418b48e7da26e5e4051dc.zip
soc/intel/cannonlake/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
Replace `LEqual(a, b)` with `a == b`. Change-Id: I844d5d2fdf0a84171385054cf7c7ca222d73c0fc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r--src/soc/intel/cannonlake/acpi/pch_hda.asl8
-rw-r--r--src/soc/intel/cannonlake/acpi/scs.asl16
2 files changed, 12 insertions, 12 deletions
diff --git a/src/soc/intel/cannonlake/acpi/pch_hda.asl b/src/soc/intel/cannonlake/acpi/pch_hda.asl
index db2d66455fb0..85182f9d0ffe 100644
--- a/src/soc/intel/cannonlake/acpi/pch_hda.asl
+++ b/src/soc/intel/cannonlake/acpi/pch_hda.asl
@@ -26,17 +26,17 @@ Device (HDAS)
*/
Method (_DSM, 4)
{
- If (LEqual (Arg0, ^UUID)) {
+ If (Arg0 == ^UUID) {
/*
* Function 0: Function Support Query
* Returns a bitmask of functions supported.
*/
- If (LEqual (Arg2, Zero)) {
+ If (Arg2 == 0) {
/*
* NHLT Query only supported for revision 1 and
* if NHLT address and length are set in NVS.
*/
- If (LEqual (Arg1, One) && LNotEqual (NHLA, Zero) && LNotEqual (NHLL, Zero)) {
+ If (Arg1 == 1 && LNotEqual (NHLA, Zero) && LNotEqual (NHLL, Zero)) {
Return (Buffer (One) { 0x03 })
} Else {
Return (Buffer (One) { 0x01 })
@@ -50,7 +50,7 @@ Device (HDAS)
*
* Returns a pointer to NHLT table in memory.
*/
- If (LEqual (Arg2, One)) {
+ If (Arg2 == 1) {
CreateQWordField (NBUF, ^NHLT._MIN, NBAS)
CreateQWordField (NBUF, ^NHLT._MAX, NMAS)
CreateQWordField (NBUF, ^NHLT._LEN, NLEN)
diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl
index 462e65a08685..4c01b482829d 100644
--- a/src/soc/intel/cannonlake/acpi/scs.asl
+++ b/src/soc/intel/cannonlake/acpi/scs.asl
@@ -73,7 +73,7 @@ Scope (\_SB.PCI0) {
*/
Method (_DSM, 4)
{
- If (LEqual (Arg0, ^DSUU)) {
+ If (Arg0 == ^DSUU) {
/* Check the revision */
If (LGreaterEqual (Arg1, Zero)) {
/*
@@ -92,8 +92,8 @@ Scope (\_SB.PCI0) {
* Bit 6 - Indicates support for HS400 mode
* Bit 9 - Indicates eMMC I/O Driver Strength
*/
- If (LEqual (Arg2, Zero)) {
- If (Lequal (VDID, 0x02c48086) ) {
+ If (Arg2 == 0) {
+ If (VDID == 0x02c48086) {
/*
* Set bit 9 for CML eMMC to indicate
* eMMC I/O driver strength is supported
@@ -111,7 +111,7 @@ Scope (\_SB.PCI0) {
* 3 - 100 ohm
* 4 - 40 ohm
*/
- If (LEqual (Arg2, 9)) {
+ If (Arg2 == 9) {
Return(Buffer() {0x4})
}
}
@@ -146,7 +146,7 @@ Scope (\_SB.PCI0) {
*/
Method (_DSM, 4)
{
- If (LEqual (Arg0, ^DSUU)) {
+ If (Arg0 == ^DSUU) {
/* Check the revision */
If (LGreaterEqual (Arg1, Zero)) {
/*
@@ -165,7 +165,7 @@ Scope (\_SB.PCI0) {
* For SD we have to support functions to
* set 1.8V signalling and 3.3V signalling [BIT4, BIT3]
*/
- If (LEqual (Arg2, Zero)) {
+ If (Arg2 == 0) {
Return (Buffer () { 0x19 })
}
/*
@@ -175,7 +175,7 @@ Scope (\_SB.PCI0) {
* UHS SD card on PCH. This is to compensate
* for the SD VR slowness.
*/
- If (LEqual (Arg2, 3)) {
+ If (Arg2 == 3) {
Sleep (100)
Return(Buffer () { 0x00 })
}
@@ -186,7 +186,7 @@ Scope (\_SB.PCI0) {
* UHS SD card on PCH. This is to compensate
* for the SD VR slowness.
*/
- If (LEqual (Arg2, 4)) {
+ If (Arg2 == 4) {
Sleep (100)
Return(Buffer () { 0x00 })
}