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| author | Nico Huber <nico.huber@secunet.com> | 2021-07-26 13:43:24 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-20 02:27:03 +0000 |
| commit | ad5b8b8ef94be2ed28a620806ca0620411578ed9 (patch) | |
| tree | 0ba09c1c45356ccb4a684d0f3ac6d7aae567d11a /src/soc/intel/cannonlake | |
| parent | 327c04a6a51432a7963ed5afcf28efb20a786d34 (diff) | |
| download | coreboot-ad5b8b8ef94be2ed28a620806ca0620411578ed9.tar.gz coreboot-ad5b8b8ef94be2ed28a620806ca0620411578ed9.tar.bz2 coreboot-ad5b8b8ef94be2ed28a620806ca0620411578ed9.zip | |
soc/intel/cannonlake: Unbreak some short lines
Change-Id: I8c8b49d519b7c6a3d1e4946818b2fc5a1dd1d3e1
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56663
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/cpu.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index be6f13c48a70..5ac7d5a405d8 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -82,20 +82,17 @@ static void configure_c_states(const config_t *const cfg) /* C-state Interrupt Response Latency Control 3 - package C8 */ msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_3_LIMIT; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); /* C-state Interrupt Response Latency Control 4 - package C9 */ msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_4_LIMIT; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); /* C-state Interrupt Response Latency Control 5 - package C10 */ msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_5_LIMIT; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } |