diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2016-10-24 15:23:40 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-10-26 01:50:36 +0200 |
| commit | aedbfc8f0917b332e648fe6c4333567bd8e58b0d (patch) | |
| tree | d56d052f2ecc6f6109a22060019e56c213a15249 /src/soc/intel/common/Makefile.inc | |
| parent | 5817a1555754709da92cae7f254d540e2b488cec (diff) | |
| download | coreboot-aedbfc8f0917b332e648fe6c4333567bd8e58b0d.tar.gz coreboot-aedbfc8f0917b332e648fe6c4333567bd8e58b0d.tar.bz2 coreboot-aedbfc8f0917b332e648fe6c4333567bd8e58b0d.zip | |
soc/intel/common: Enable support to write protect SPI flash range
Write-protect SPI flash range provided by caller by using a free Flash
Protected Range (FPR) register. This expects SoC to define a callback
for providing information about the first FPR register address and
maximum number of FPRs supported.
BUG=chrome-os-partner:58896
Change-Id: I4e34ede8784e5587a5e08ffa10e20d2d14e20add
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17115
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/common/Makefile.inc')
| -rw-r--r-- | src/soc/intel/common/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 13ba21bcbeb9..888c657f3e74 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -19,6 +19,7 @@ postcar-y += util.c ramstage-y += hda_verb.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_SPI_PROTECT) += spi.c ramstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c ramstage-y += util.c |