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| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2022-01-25 00:15:17 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-06 17:32:31 +0000 |
| commit | 2c2706cceff42e019dcf0bb64fafd754ace8b707 (patch) | |
| tree | ee704cd68418d7a922e33ad3dc75b00702f28877 /src/soc/intel/common/basecode | |
| parent | bd656b4e4c46cb4d9c5601837f5e122a8b937061 (diff) | |
| download | coreboot-2c2706cceff42e019dcf0bb64fafd754ace8b707.tar.gz coreboot-2c2706cceff42e019dcf0bb64fafd754ace8b707.tar.bz2 coreboot-2c2706cceff42e019dcf0bb64fafd754ace8b707.zip | |
soc/intel/common: Add support to control coreboot and Intel SoC features
The patch adds a framework to control coreboot and Intel SoC features
dynamically. BIOS reads control information from OEM Section in the
Descriptor Region and control the developer selected features.
With the feature, debug team can control the selected SoC and coreboot
features without rebuilding coreboot.
In order to enable the feature, SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE has
to be selcted from mainboard.
The OEM section starts from offset:0xf00 till end of the Descriptor
Region(0xfff).
BUG=b:153410586
BRANCH=None
TEST=Verified CSE firmware update functionality on brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Diffstat (limited to 'src/soc/intel/common/basecode')
5 files changed, 71 insertions, 0 deletions
diff --git a/src/soc/intel/common/basecode/Kconfig b/src/soc/intel/common/basecode/Kconfig index 9e0f788eb414..97309854cf41 100644 --- a/src/soc/intel/common/basecode/Kconfig +++ b/src/soc/intel/common/basecode/Kconfig @@ -2,3 +2,9 @@ config SOC_INTEL_COMMON_BASECODE bool help Common coreboot stages and non-IP block for Intel platform + +if SOC_INTEL_COMMON_BASECODE + +source "src/soc/intel/common/basecode/*/Kconfig" + +endif diff --git a/src/soc/intel/common/basecode/debug/Kconfig b/src/soc/intel/common/basecode/debug/Kconfig new file mode 100644 index 000000000000..f72055b67239 --- /dev/null +++ b/src/soc/intel/common/basecode/debug/Kconfig @@ -0,0 +1,6 @@ +config SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE + bool + default n + help + Driver to control runtime features of Intel SoC & coreboot. For example, controlling + the CSE firmware update feature without rebuilding the code. diff --git a/src/soc/intel/common/basecode/debug/Makefile.inc b/src/soc/intel/common/basecode/debug/Makefile.inc new file mode 100644 index 000000000000..f783c8d14a10 --- /dev/null +++ b/src/soc/intel/common/basecode/debug/Makefile.inc @@ -0,0 +1 @@ +romstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE) += debug_feature.c diff --git a/src/soc/intel/common/basecode/debug/debug_feature.c b/src/soc/intel/common/basecode/debug/debug_feature.c new file mode 100644 index 000000000000..5cdbaf7e5af4 --- /dev/null +++ b/src/soc/intel/common/basecode/debug/debug_feature.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <boot_device.h> +#include <commonlib/region.h> +#include <intelbasecode/debug_feature.h> +#include <console/console.h> +#include <fmap.h> + +#define SI_DESC_OEM_SECTION_OFFSET 0xF00 +#define PRE_MEM_FEATURE_CTRL_OFFSET SI_DESC_OEM_SECTION_OFFSET +#define PRE_MEM_FEATURE_CTRL_SZ 64 +#define SI_DESC_REGION_SZ 4096 + +struct pre_mem_ft { + uint8_t reserved[64]; +}; + +static struct pre_mem_ft pre_mem_debug; + +_Static_assert(sizeof(struct pre_mem_ft) % 64 == 0 && sizeof(struct pre_mem_ft) <= 256, + "sizeof(struct pre_mem_ft) must be a multiple of 64 bytes and up to 256 bytes"); + +uint8_t pre_mem_debug_init(void) +{ + struct region_device desc_rdev; + const struct region_device *boot_device = boot_device_ro(); + + if (!boot_device) { + printk(BIOS_ERR, "Failed to get RW boot device\n"); + return 1; + } + + if (rdev_chain(&desc_rdev, boot_device, 0, SI_DESC_REGION_SZ)) { + printk(BIOS_ERR, "Failed to get description region device\n"); + return 1; + } + + if (rdev_readat(&desc_rdev, &pre_mem_debug, PRE_MEM_FEATURE_CTRL_OFFSET, + PRE_MEM_FEATURE_CTRL_SZ) != PRE_MEM_FEATURE_CTRL_SZ) { + printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n"); + return 1; + } + return 0; +} diff --git a/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h b/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h new file mode 100644 index 000000000000..fabf27ddd80c --- /dev/null +++ b/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE_H +#define SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE_H + +#include <types.h> + +/* + * Reads OEM Section area in the Descriptor Region and + * populates pre_mem_debug structure. + */ +uint8_t pre_mem_debug_init(void); + +#endif |