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| author | Uwe Poeche <uwe.poeche@siemens.com> | 2022-03-28 12:39:01 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-18 11:14:09 +0000 |
| commit | 539fd2ac5a0f510d8434d4cc8a597f092325b8c8 (patch) | |
| tree | 26b7b42ba97288d14ff218c4b49d2fc741a22d21 /src/soc/intel/common/block/cpu | |
| parent | db9873b69c52cc1eac5bfef72228f071e303a78f (diff) | |
| download | coreboot-539fd2ac5a0f510d8434d4cc8a597f092325b8c8.tar.gz coreboot-539fd2ac5a0f510d8434d4cc8a597f092325b8c8.tar.bz2 coreboot-539fd2ac5a0f510d8434d4cc8a597f092325b8c8.zip | |
intel/common/block: Provide RAPL and min clock ratio switches in common
There are two APL specific config switches for RAPL and min. cpu clock
(APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO). These switches
could be used in future in other CPU platforms. Move them to common code
instead of having them just for one SOC.
Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings
(MSR0x610) do not change with this patch applied on mc_apl{1,4,5}
mainboard.
Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/common/block/cpu')
| -rw-r--r-- | src/soc/intel/common/block/cpu/Kconfig | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 378b6a244cad..17240ac91f93 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -136,3 +136,21 @@ config SOC_INTEL_NO_BOOTGUARD_MSR help Select this on platforms that do not support Bootguard related MSRs 0x139, MSR_BC_PBEC and 0x13A, MSR_BOOT_GUARD_SACM_INFO. + +config SOC_INTEL_DISABLE_POWER_LIMITS + bool + default n + help + Select this if the Running Average Power Limits (RAPL) algorithm + for constant power management is not needed. + +config SOC_INTEL_SET_MIN_CLOCK_RATIO + bool + depends on !SOC_INTEL_DISABLE_POWER_LIMITS + default n + help + If the power budget of the mainboard is limited, it can be useful to + limit the CPU power dissipation at the cost of performance by setting + the lowest possible CPU clock. Enable this option if you need smallest + possible CPU clock. This setting can be overruled by the OS if it has an + p-state driver which can adjust the clock to its need. |