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author | Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> | 2023-05-30 12:30:36 -0700 |
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committer | Martin L Roth <gaumless@gmail.com> | 2023-06-06 17:34:53 +0000 |
commit | e4893d6b80806b9748a3593310278e65a3f63dee (patch) | |
tree | 3cf3986b4c1b5239910f536cb1f783d9e04a8965 /src/soc/intel/common/block/crashlog | |
parent | d7ad1409b955f83e40da3b648e85bc3cc2b919a8 (diff) | |
download | coreboot-e4893d6b80806b9748a3593310278e65a3f63dee.tar.gz coreboot-e4893d6b80806b9748a3593310278e65a3f63dee.tar.bz2 coreboot-e4893d6b80806b9748a3593310278e65a3f63dee.zip |
soc/intel/common/crashlog: Add support for IOE die
Intel Meteor Lake SOC has a separate I/O Expander (IOE) die.
SRAM from this IOE die contains crashlog records for the IPs
of the IOE die.
This patch adds functions with empty implementation using
__weak attribute for IOE die related crashlog, changes common
data structures while maintaining backwards compatibility,
and support for filling IOE crashlog records, guarded by
SOC_INTEL_IOE_DIE_SUPPORT config and makes cl_get_pmc_sram_data
function as weak because it needs SOC specific implementation.
Bug=b:262501347
TEST=Able to build. With Meteor Lake SOC related patch, able to
capture and decode crashlog
Change-Id: Id90cf0095258c4f7003e4c5f2564bb763e687b75
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75475
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/crashlog')
-rw-r--r-- | src/soc/intel/common/block/crashlog/crashlog.c | 41 |
1 files changed, 40 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/crashlog/crashlog.c b/src/soc/intel/common/block/crashlog/crashlog.c index 4b72599bfd46..5b098bb583e6 100644 --- a/src/soc/intel/common/block/crashlog/crashlog.c +++ b/src/soc/intel/common/block/crashlog/crashlog.c @@ -23,6 +23,11 @@ u32 __weak cl_get_cpu_bar_addr(void) return 0; } +int __weak cl_get_ioe_record_size(void) +{ + return 0; +} + u32 __weak cl_get_cpu_tmp_bar(void) { return 0; @@ -43,6 +48,11 @@ bool __weak cl_pmc_sram_has_mmio_access(void) return false; } +bool __weak cl_ioe_sram_has_mmio_access(void) +{ + return false; +} + bool __weak cpu_crashlog_support(void) { return false; @@ -63,12 +73,19 @@ bool __weak cl_pmc_data_present(void) return false; } +bool __weak cl_ioe_data_present(void) +{ + return false; +} + __weak void reset_discovery_buffers(void) {} __weak void update_new_pmc_crashlog_size(u32 *pmc_crash_size) {} __weak void update_new_cpu_crashlog_size(u32 *cpu_crash_size) {} +__weak void update_new_ioe_crashlog_size(u32 *ioe_crash_size) {} + pmc_ipc_discovery_buf_t __weak cl_get_pmc_discovery_buf(void) { pmc_ipc_discovery_buf_t discov_buf; @@ -303,7 +320,7 @@ bool cl_copy_data_from_sram(u32 src_bar, return true; } -void cl_get_pmc_sram_data(void) +void __weak cl_get_pmc_sram_data(void) { u32 *dest = NULL; u32 tmp_bar_addr = cl_get_cpu_tmp_bar(); @@ -518,3 +535,25 @@ bool cl_fill_pmc_records(void *cl_record) return true; } + +bool cl_fill_ioe_records(void *cl_record) +{ + void *cl_src_addr = NULL; + + u32 m_ioe_crashLog_size = cl_get_ioe_record_size(); + + if (!cl_ioe_data_present() || m_ioe_crashLog_size == 0) { + printk(BIOS_DEBUG, "IOE crashLog not present, skipping.\n"); + return false; + } + + printk(BIOS_DEBUG, "IOE PMC crash data collection.\n"); + cl_src_addr = cbmem_find(CBMEM_ID_IOE_CRASHLOG); + if (!cl_src_addr) { + printk(BIOS_DEBUG, "IOE crash data, CBMEM not found\n"); + return false; + } + memcpy(cl_record, cl_src_addr, m_ioe_crashLog_size); + + return true; +} |