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| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2020-10-18 20:14:07 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-11-18 01:26:44 +0000 |
| commit | 361e3646357504ef8843e3f85b35a1a966b88fe1 (patch) | |
| tree | 88c323733df9f243d970d98acf79c63d59e75eb7 /src/soc/intel/common/block/cse/Kconfig | |
| parent | 0759346cd6c0dcfd300eeca216e0a2d2ed76a827 (diff) | |
| download | coreboot-361e3646357504ef8843e3f85b35a1a966b88fe1.tar.gz coreboot-361e3646357504ef8843e3f85b35a1a966b88fe1.tar.bz2 coreboot-361e3646357504ef8843e3f85b35a1a966b88fe1.zip | |
soc/intel/common: Move CSE RW into new FMAP region to optimize boot time
CSE RW blob which will be used by coreboot to update CSE's RW partition,
is packed part of FW_MAIN_A and FW_MAIN_B. This will increase the size of
FW_MAIN_A and FW_MAIN_B. So, accordingly load and hash calculation of
FW_MAIN_A (or FW_MAIN_B) increases during verstage. It increases the boot
time by around 300ms.
The patch address the boot time by pulling CSE RW blob outside of
FW_MAIN_A and FW_MAIN_B. So, it creates new FMAP region within
RW_SECTION_A and RW_SECTION_B and adds CSE RW blob in the new regions
(ME_RW_A and ME_RW_B) as a CBFS file.
Boot Time Measurement details when CSE RW blob is added in the
ME_RW_A and ME_RW_B.
--------------------------------------------------------
| Platform | Old Boot Time | New Boot Time |
--------------------------------------------------------
| JSL | 1.3s | 1.06s |
--------------------------------------------------------
| TGL | 1.63s | 1.36s |
--------------------------------------------------------
Changes:
1. Makefile change to accommodate CSE RW blob into ME_RW_A/ME_RW_B
2. Kconfig change to define CBFS name and default file name for RW blob
metadata.
3. CSE Lite Driver
BUG=b:169077783
TEST=Verified on JSL & TGL platforms
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If043c9cb99fb822b62633591bf9c5bd75dfe8349
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/intel/common/block/cse/Kconfig')
| -rw-r--r-- | src/soc/intel/common/block/cse/Kconfig | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index b427b15b7061..ee6ce68c1f37 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -35,6 +35,20 @@ config SOC_INTEL_CSE_FMAP_NAME help Name of CSE region in FMAP +config SOC_INTEL_CSE_RW_A_FMAP_NAME + string "Location of CSE RW A in FMAP" + depends on SOC_INTEL_CSE_LITE_SKU + default "ME_RW_A" + help + Name of CSE RW A region in FMAP + +config SOC_INTEL_CSE_RW_B_FMAP_NAME + string "Location of CSE RW B in FMAP" + depends on SOC_INTEL_CSE_LITE_SKU + default "ME_RW_B" + help + Name of CSE RW B region in FMAP + config SOC_INTEL_CSE_RW_CBFS_NAME string "CBFS entry name for CSE RW blob" default "me_rw" |