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| author | Furquan Shaikh <furquan@google.com> | 2021-10-09 00:08:56 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2021-10-19 16:09:49 +0000 |
| commit | 3f0d64329cbf7c37ace03c98113f76e3862b11e4 (patch) | |
| tree | e0b54471ca7f819b3b5c29ce17f44273cb90530f /src/soc/intel/common/block/cse/Kconfig | |
| parent | 0a0182e13d2124de3328a90b4a4d556f60d3bf8f (diff) | |
| download | coreboot-3f0d64329cbf7c37ace03c98113f76e3862b11e4.tar.gz coreboot-3f0d64329cbf7c37ace03c98113f76e3862b11e4.tar.bz2 coreboot-3f0d64329cbf7c37ace03c98113f76e3862b11e4.zip | |
soc/intel/common/cse: Support RW update when stitching CSE binary
This change updates the STITCH_ME_BIN path to enable support for
including CSE RW update in CBFS. CSE_RW_FILE is set to either
CONFIG_SOC_INTEL_CSE_RW_FILE or CSE_BP2_BIN depending upon the
selection of STITCH_ME_BIN config.
BUG=b:189177580
Change-Id: I0478f6b2a3342ed29c7ca21aa8e26655c58265f4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/cse/Kconfig')
| -rw-r--r-- | src/soc/intel/common/block/cse/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 4305deaf2b64..d1f4d333425e 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -64,7 +64,7 @@ config SOC_INTEL_CSE_RW_VERSION_CBFS_NAME CBFS name for Intel CSE CBFS RW version file config SOC_INTEL_CSE_RW_FILE - string "Intel CSE CBFS RW path and filename" if SOC_INTEL_CSE_RW_UPDATE + string "Intel CSE CBFS RW path and filename" if SOC_INTEL_CSE_RW_UPDATE && !STITCH_ME_BIN default "" help Intel CSE CBFS RW blob path and file name |