soc/intel/common/cse: Add support for stitching CSE components

This change adds support for allowing mainboards to stitch CSE
components during build time instead of adding a pre-built CSE
binary. Several Kconfig options are added to allow mainboard to
provide the file names for different CSE region components. This makes
use of the newly added cse_serger and cse_fpt tools to create
following partitions:
1. BP1 - RO
2. BP2 - RW
3. Layout

In addition to this, it accepts CSE data partition as an input using
Kconfig CSE_DATA_FILE. All these partitions are then assembled
together as per the following mainboard FMAP regions:
1. BP1(RO) : CSE_RO
2. BP2(RW) : CSE_RW
3. Layout  : CSE_LAYOUT
4. Data    : CSE_DATA

Finally, it generates the target $(OBJ_ME_BIN) which is used to put
together the binary in final coreboot.rom image.

Several helper functions are added to soc/intel/Makefile.inc to allow
SoCs to define which components use:
1. Decomposed files: Files decomposed from Intel release CSE binary in
FPT format.
2. Input files: Mainboard provided input files using corresponding
Kconfigs.
3. Dummy: Components that are required to have dummy entries in
BPDT header.

These helpers are added to soc/intel/Makefile.inc to ensure that the
functions are defined by the time the invocations are encountered in
SoC Makefile.inc.

BUG=b:189177580

Change-Id: I8359cd49ad256703285e55bc4319c6e9c9fccb67
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

1 files changed, 64 insertions, 0 deletions

diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index e06895080e99..4305deaf2b64 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -85,3 +85,67 @@ config SOC_INTEL_CSE_SET_EOP
 	  This config ensures coreboot will send the CSE the End-of-POST message
 	  just prior to loading the payload. This is a security feature so the
 	  CSE will no longer respond to Pre-Boot commands.
+
+if STITCH_ME_BIN
+
+config CSE_COMPONENTS_PATH
+	string "Path to directory containing all CSE input components to stitch"
+	default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/firmware"
+	help
+	  This is the file path containing all the input CSE component files.
+	  These will be used by cse_serger tool to stitch CSE image.
+
+config CSE_FPT_FILE
+	string "Name of CSE FPT file"
+	default "cse_fpt.bin"
+	help
+	  This file is the CSE input binary as released by Intel in a CSE kit.
+
+config CSE_DATA_FILE
+	string "Name of CSE data file"
+	default "cse_data.bin"
+	help
+	  This file is the CSE data binary typically generated by Intel FIT tool.
+
+config CSE_PMCP_FILE
+	string "Name of PMC file"
+	default "pmc.bin"
+	help
+	  This file is the PMC input binary as released by Intel in a CSE kit.
+
+config CSE_IOMP_FILE
+	string "Name of IOM file"
+	default "iom.bin"
+	help
+	  This file is the IOM input binary as released by Intel in a CSE kit.
+
+config CSE_TBTP_FILE
+	string "Name of TBT file"
+	default "tbt.bin"
+	help
+	  This file is the TBT input binary as released by Intel in a CSE kit.
+
+config CSE_NPHY_FILE
+	string "Name of NPHY file"
+	default "nphy.bin"
+	help
+	  This file is the NPHY input binary as released by Intel in a CSE kit.
+
+config CSE_PCHC_FILE
+	string "Name of PCHC file"
+	default "pchc.bin"
+	help
+	  This file is the PCHC input binary as released by Intel in a CSE kit.
+
+config CSE_IUNP_FILE
+	string "Name of IUNIT file"
+	default "iunit.bin"
+	help
+	  This file is the PCHC input binary as released by Intel in a CSE kit.
+
+config CSE_BPDT_VERSION
+	string
+	help
+	  This config indicates the BPDT version used by CSE for a given SoC.
+
+endif