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authorAngel Pons <th3fanbus@gmail.com>2022-08-13 19:50:28 +0200
committerMartin Roth <martin.roth@amd.corp-partner.google.com>2022-08-14 21:18:56 +0000
commit2e8e0601fda4a5a1b2a3b1f18fd1c20608e423df (patch)
tree9e7bb41a976294477e1474bfdb63330fc40e69a2 /src/soc/intel/common/block/cse/cse_lite.c
parent492ce254753de3ac1ae5040dd41c91dd7165e3e6 (diff)
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soc/intel/common/block/cse: Tidy up table in comment
Adjust an ASCII art table so that it looks good: consistent padding and aligned table borders. Change-Id: I26196f969406e03f320256b0c3a337282f636914 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66707 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/common/block/cse/cse_lite.c')
-rw-r--r--src/soc/intel/common/block/cse/cse_lite.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 2e8a868dc822..40ae9953ec68 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -34,9 +34,9 @@
* CSE Firmware supports 3 boot partitions. For CSE Lite SKU, only 2 boot partitions are
* used and 3rd boot partition is set to BP_STATUS_PARTITION_NOT_PRESENT.
* CSE Lite SKU Image Layout:
- * ------------- ------------------ --------------------
- * |CSE REGION | => | RO | DATA | RW | => | BP1 | DATA | BP2 |
- * ------------- ------------------ --------------------
+ * +------------+ +----+------+----+ +-----+------+-----+
+ * | CSE REGION | => | RO | DATA | RW | => | BP1 | DATA | BP2 |
+ * +------------+ +----+------+----+ +-----+------+-----+
*/
#define CSE_MAX_BOOT_PARTITIONS 3