soc/intel/common: Use heci_reset() in the CSE TX and RX flows

The patch implements error handling as per the ME BWG guide. The BWG
recommends HECI interface reset if there is a timeout or malformed
response is received from the CSE. Also, the patch triggers HECI
interface reset if the CSE link state is not ready in the heci_send()
API.

TEST=Verify HECI Interface reset in the simulated error scenarios.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I3e4a97800cbc5d95b8fd259e6e34a32fc82d8563
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

1 files changed, 6 insertions, 1 deletions

diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 810973bf965c..bbd8afc50318 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -458,6 +458,8 @@ heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t client_addr)
 			return CSE_TX_RX_SUCCESS;
 	}
 
+	printk(BIOS_DEBUG, "HECI: Trigger HECI reset\n");
+	heci_reset();
 	return CSE_TX_ERR_CSE_NOT_READY;
 }
 
@@ -548,7 +550,7 @@ static enum cse_tx_rx_status heci_receive(void *buff, size_t *maxlen)
 			ret = recv_one_message(&hdr, p, left, &received);
 			if (ret) {
 				printk(BIOS_ERR, "HECI: Failed to receive!\n");
-				return ret;
+				goto CSE_RX_ERR_HANDLE;
 			}
 			left -= received;
 			p += received;
@@ -563,6 +565,9 @@ static enum cse_tx_rx_status heci_receive(void *buff, size_t *maxlen)
 		}
 	}
 
+CSE_RX_ERR_HANDLE:
+	printk(BIOS_DEBUG, "HECI: Trigger HECI Reset\n");
+	heci_reset();
 	return CSE_RX_ERR_CSE_NOT_READY;
 }