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| author | Subrata Banik <subratabanik@google.com> | 2023-06-13 00:44:44 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-06-15 07:38:47 +0000 |
| commit | 272ce9a5796ef63516733ab2c25ece39d0ab194f (patch) | |
| tree | af407229402091c4c8e9bf414ba8a4d320c6ac55 /src/soc/intel/common/block/cse | |
| parent | cacdb859795a2861223275dde99b1f744130ba2a (diff) | |
| download | coreboot-272ce9a5796ef63516733ab2c25ece39d0ab194f.tar.gz coreboot-272ce9a5796ef63516733ab2c25ece39d0ab194f.tar.bz2 coreboot-272ce9a5796ef63516733ab2c25ece39d0ab194f.zip | |
{driver, mb, soc}: Rename Intel CSE FPT config to ISH FW version config
This patch renames `SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION` config
to `SOC_INTEL_STORE_ISH_FW_VERSION` to ensure the usage of this config
is clear.
Any platform would like to fetch the currently running ISH firmware
version should select this configuration.
TEST=Able to build and boot google/marasov.
Change-Id: Ie503d6a5bf5bd0d3d561355b592e75b22c910bf5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75767
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/soc/intel/common/block/cse')
| -rw-r--r-- | src/soc/intel/common/block/cse/Kconfig | 19 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cse/cse_lite.c | 2 |
2 files changed, 11 insertions, 10 deletions
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 26c623fe8d9c..d809e03e9f2f 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -45,22 +45,23 @@ config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented) to make `HECI1` device disable using private configuration register (PCR) write. -config SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION +config SOC_INTEL_STORE_ISH_FW_VERSION bool default n depends on DRIVERS_INTEL_ISH help - This configuration option stores CSE FPT partitions' version in CBMEM memory. - This information can be used to identify the currently running firmware partition + This configuration option stores ISH version in CBMEM area. + This information can be used to identify the currently running ISH firmware version. - The cost of sending HECI command to read the CSE FPT is significant (~200ms) - hence, the idea is to read the CSE RW version on every cold reset (to cover - the CSE update scenarios) and store into CBMEM to avoid the cost of resending - the HECI command in all consecutive warm boots. + ISH BUP is sitting inside the CSE firmware partition. The way to retrieve the + ISH version is by sending the HECI command to read the CSE FPT. The cost of sending + HECI command to read the CSE FPT is significant (~200ms) hence, the idea is to + read the CSE RW version on every cold reset (to cover the CSE update scenarios) + and store into CBMEM to avoid the cost of resending the HECI command in all + consecutive warm boots. - Later boot stages can just read the CBMEM ID to retrieve the ISH version if - required. + Later boot stages can just read the CBMEM ID to retrieve the ISH version. Additionally, ensure this feature is platform specific hence, only enabled for the platform that would like to store the ISH version into the CBMEM and diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 733f68bc38c8..7063ecb80a12 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1307,7 +1307,7 @@ static void ramstage_cse_misc_ops(void *unused) * Store the CSE/ISH RW Firmware Version into CBMEM if ISH partition * is available */ - if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION) && + if (CONFIG(SOC_INTEL_STORE_ISH_FW_VERSION) && soc_is_ish_partition_enabled()) { store_cse_rw_fw_version(); store_ish_version(); |