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| author | Subrata Banik <subratabanik@google.com> | 2023-04-28 00:52:23 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-05-06 05:36:44 +0000 |
| commit | 792ce8197355d01093c26335906bec8c5e7a2761 (patch) | |
| tree | 4d1d081ccc7bb3ddfdd9de5663cefb7f58675f1b /src/soc/intel/common/block/cse | |
| parent | 199728b4d2aade12c649e6a07579436ec36ca623 (diff) | |
| download | coreboot-792ce8197355d01093c26335906bec8c5e7a2761.tar.gz coreboot-792ce8197355d01093c26335906bec8c5e7a2761.tar.bz2 coreboot-792ce8197355d01093c26335906bec8c5e7a2761.zip | |
soc/intel: Do CSE sync in romstage, unless ramstage chooses otherwise
This patch makes CSE sync in romstage default enabled unless ramstage
config (SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) chooses to override it.
TEST=Able to build google/marasov with this change where CSE sync is
performed early inside romstage.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3f5017fbcf917201eaf8233089050bd31c3d1917
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Diffstat (limited to 'src/soc/intel/common/block/cse')
| -rw-r--r-- | src/soc/intel/common/block/cse/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 1eb3eff8f16f..26c623fe8d9c 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -248,7 +248,7 @@ config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 config SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE bool - default y + default !SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_COMPRESS_ME_RW help Use default flow of CSE FW Update in romstage when uncompressed ME_RW blobs are used. |