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| author | Sean Rhodes <sean@starlabs.systems> | 2023-04-14 12:25:28 +0100 |
|---|---|---|
| committer | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2023-05-11 14:54:54 +0000 |
| commit | 88ade91073ac7e6f550ad9e3f5239cc76cb6d202 (patch) | |
| tree | a5d92eaf8970d06037732aff9d56e2b94ab0b998 /src/soc/intel/common/block/cse | |
| parent | 8d1051f4aa0ab2d20df4924a7a13a82922153663 (diff) | |
| download | coreboot-88ade91073ac7e6f550ad9e3f5239cc76cb6d202.tar.gz coreboot-88ade91073ac7e6f550ad9e3f5239cc76cb6d202.tar.bz2 coreboot-88ade91073ac7e6f550ad9e3f5239cc76cb6d202.zip | |
soc/intel/common: Fix long delay when ME is disabled
If the ME is disabled with the `me_state` CMOS setting, boot
times are approximately 5 seconds longer:
942:before sending EOP to ME 1,240,773 (5,599)
943:after sending EOP to ME 6,263,951 (5,023,177)
Total Time: 6,167,443
This is because the current code only checks if the ME is
disabled for CSE LITE SKUs. With this patch, boot times are
approximately 5 seconds quicker:
Total Time: 1,143,932
Tested on `starbook/adl` and `starbook/tgl`.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I182f30d4fbf43955747c6a7a0b284a43f9c5e4ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/common/block/cse')
| -rw-r--r-- | src/soc/intel/common/block/cse/cse_eop.c | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index dd67e595bbb3..135bcb7be29a 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -269,21 +269,33 @@ static void do_send_end_of_post(bool wait_for_completion) /* * Don't send EOP if the following conditions are met: + * CSE Lite: * 1. "The platform is running CSE-Lite SKU" AND * 2. 'The CSE is running the RO FW" AND * 3. "The board is in recovery mode" * + * Other CSE Type: + * 1. "The board is in recovery mode" + * * The above conditions summarize that the CSE is in "SOFT TEMP DISABLE" state, * hence, don't send the EOP command to CSE. */ static bool is_cse_eop_supported(void) { - if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && vboot_recovery_mode_enabled() && + /* CSE Lite */ + if ((CONFIG(SOC_INTEL_CSE_LITE_SKU) && vboot_recovery_mode_enabled()) && cse_is_hfs1_com_soft_temp_disable()) { - printk(BIOS_INFO, "HECI: coreboot in recovery mode; found CSE in expected SOFT " - "TEMP DISABLE state, skipping EOP\n"); + printk(BIOS_INFO, "HECI: coreboot in recovery mode; found CSE Lite in expected " + "SOFT TEMP DISABLE state, skipping EOP\n"); return false; } + /* Other CSE Type */ + if (cse_is_hfs1_com_soft_temp_disable()) { + printk(BIOS_INFO, "HECI: coreboot in recovery mode; found CSE in expected " + "SOFT TEMP DISABLE state, skipping EOP\n"); + return false; + } + return true; } |