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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-06-12 22:06:09 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-14 09:30:24 +0000 |
| commit | 68c851bcd702e7816cdb6e504f7386ec404ecf13 (patch) | |
| tree | 4f54fa935d738ff5e6fc473ba37bfc03a8ecb2ef /src/soc/intel/common/block/fast_spi/fast_spi.c | |
| parent | c8a649c08f92d4d2255626da4e1cd7a6d71469e7 (diff) | |
| download | coreboot-68c851bcd702e7816cdb6e504f7386ec404ecf13.tar.gz coreboot-68c851bcd702e7816cdb6e504f7386ec404ecf13.tar.bz2 coreboot-68c851bcd702e7816cdb6e504f7386ec404ecf13.zip | |
src: Get rid of device_t
Use of device_t is deprecated.
Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/common/block/fast_spi/fast_spi.c')
| -rw-r--r-- | src/soc/intel/common/block/fast_spi/fast_spi.c | 30 |
1 files changed, 25 insertions, 5 deletions
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index b13408af7bab..e7f81fc32345 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -34,7 +34,11 @@ */ void *fast_spi_get_bar(void) { - device_t dev = PCH_DEV_SPI; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_SPI; +#else + struct device *dev = PCH_DEV_SPI; +#endif uintptr_t bar; bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -51,7 +55,11 @@ void *fast_spi_get_bar(void) */ void fast_spi_init(void) { - device_t dev = PCH_DEV_SPI; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_SPI; +#else + struct device *dev = PCH_DEV_SPI; +#endif uint8_t bios_cntl; bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL); @@ -71,7 +79,11 @@ void fast_spi_init(void) */ static void fast_spi_set_bios_control_reg(uint8_t bios_cntl_bit) { - device_t dev = PCH_DEV_SPI; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_SPI; +#else + struct device *dev = PCH_DEV_SPI; +#endif uint8_t bc_cntl; assert((bios_cntl_bit & (bios_cntl_bit - 1)) == 0); @@ -253,7 +265,11 @@ void fast_spi_cache_bios_region(void) */ void fast_spi_early_init(uintptr_t spi_base_address) { - device_t dev = PCH_DEV_SPI; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_SPI; +#else + struct device *dev = PCH_DEV_SPI; +#endif uint8_t pcireg; /* Assign Resources to SPI Controller */ @@ -285,7 +301,11 @@ bool fast_spi_wpd_status(void) /* Enable SPI Write Protect. */ void fast_spi_enable_wp(void) { - device_t dev = PCH_DEV_SPI; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_SPI; +#else + struct device *dev = PCH_DEV_SPI; +#endif uint8_t bios_cntl; bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL); |