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| author | Subrata Banik <subratabanik@google.com> | 2023-08-13 13:03:50 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-08-18 19:58:24 +0000 |
| commit | 65a6d1714d7d986cb95be2190518a80562d5e509 (patch) | |
| tree | 4f793630caac1bbc357419968c23326149103943 /src/soc/intel/common/block/include/intelblocks/cse.h | |
| parent | 5ba16d02b6fb27c95c80ce12d976882812e9cfe0 (diff) | |
| download | coreboot-65a6d1714d7d986cb95be2190518a80562d5e509.tar.gz coreboot-65a6d1714d7d986cb95be2190518a80562d5e509.tar.bz2 coreboot-65a6d1714d7d986cb95be2190518a80562d5e509.zip | |
soc/intel/cmn/cse: Refactor CSE RW FW Version implementation
This patch introduces a CSE firmware specific data in order
to store Intel CSE and associated firmware related information which
requires a sync between Pre-RAM and Post-RAM phase.
This information will be used further to retrieve currently running
CSE RW firmware instead of fetching the version information by sending
a HECI cmd (which consumes 7ms-15ms depending upon the CSE operational
state).
Current implementation attempts to simply the CSE RW FW version store
and retrieval operations as below
* CSE sync in romstage (aka Pre-RAM) - Relying on .bss segment to store
the CSE info data in absence of real physical memory and sync back into
the CBMEM once available (after FSP-M exits).
* CSE sync in ramstage (aka Post-RAM) - Directly stored the CSE RW
version into the CBMEM (as CBMEM is online).
BUG=b:285405031
TEST=Able to build and boot google/rex. Verified CSE RW FW version
(for LITE SKU) is getting displayed without impacting the boot time.
w/o this patch:
10:start of ramstage 722,257 (43)
17:starting LZ4 decompress (ignore for x86) 723,777 (1,520)
w/ this patch:
10:start of ramstage 722,257 (43)
17:starting LZ4 decompress (ignore for x86) 723,777 (1,520)
Change-Id: Ia873af512851a682cf1fac0e128d842562a316ab
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77174
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks/cse.h')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 636b1f406429..ae9fe941c675 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -160,6 +160,13 @@ struct cse_fw_partition_info { struct cse_fw_ish_version_info ish_partition_info; }; +/* CSE Specific Information */ +struct cse_specific_info { + struct cse_fw_partition_info cse_fwp_version; + bool cse_downgrade_requested; + uint32_t crc; +}; + /* CSE RX and TX error status */ enum cse_tx_rx_status { /* |