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author | Michael Niewöhner <foss@mniewoehner.de> | 2021-01-17 01:42:15 +0100 |
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committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-01-20 18:29:06 +0000 |
commit | 71624cd94f85b8cdad7ae59e9af6a9a509ba51c3 (patch) | |
tree | a081ab3a7a6423b9caba8df89ed061d8e0ab1e37 /src/soc/intel/common/block/include/intelblocks/lpc_lib.h | |
parent | 2cbe3df2cd8f827c0ef67c5e8fd0688dd0aee103 (diff) | |
download | coreboot-71624cd94f85b8cdad7ae59e9af6a9a509ba51c3.tar.gz coreboot-71624cd94f85b8cdad7ae59e9af6a9a509ba51c3.tar.bz2 coreboot-71624cd94f85b8cdad7ae59e9af6a9a509ba51c3.zip |
soc/intel/*: drop broken LPC mmio code
The code for setting the LPC generic memory range uses an array of fixed
address ranges not needing explicit decoding, to decide if the address
needs to be written to the LGMR register. Most platforms only mistakenly
add the PCH reserved mmio range, that is not decoded generally,
effectively breaking the mechanism. Only APL uses the array correctly.
That code, in it's current state, does not work (except for APL) and
currently, there is not a single user. Thus, drop it before people start
using it.
Change-Id: I723415fedd1b1d95c502badf7b0510a1338b11ac
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks/lpc_lib.h')
-rw-r--r-- | src/soc/intel/common/block/include/intelblocks/lpc_lib.h | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index 82cba8ec7f5d..542281ed43b3 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -45,11 +45,6 @@ enum serirq_mode { SERIRQ_OFF, }; -struct lpc_mmio_range { - uintptr_t base; - size_t size; -}; - /* * Enable fixed IO ranges to LPC. IOE_* macros can be OR'ed together. * Output:I/O Enable Bits @@ -65,8 +60,6 @@ void lpc_open_pmio_window(uint16_t base, uint16_t size); void lpc_close_pmio_windows(void); /* Open a generic MMIO window to the LPC bus. One window is available. */ void lpc_open_mmio_window(uintptr_t base, size_t size); -/* Returns true if given window is decoded to LPC via a fixed range. */ -bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size); /* Init SoC Specific LPC features. Common definition will be weak and each soc will need to define the init. */ void lpc_soc_init(struct device *dev); @@ -74,8 +67,6 @@ void lpc_soc_init(struct device *dev); void pch_lpc_soc_fill_io_resources(struct device *dev); /* Init LPC GPIO pads */ void lpc_configure_pads(void); -/* Get SoC specific MMIO ranges */ -const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void); /* Set LPC BIOS Control BILD bit. */ void lpc_set_bios_interface_lock_down(void); /* Set LPC BIOS Control LE bit. */ |