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| author | Kane Chen <kane.chen@intel.com> | 2019-08-23 12:03:05 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-08-28 09:22:34 +0000 |
| commit | 01ebc74d5620f7cdbf3e51fae8e720e027d55f39 (patch) | |
| tree | 7c4b3715f0e59b35da41563e739ea1811ecececc /src/soc/intel/common/block/include | |
| parent | fdd0e9b38f02f5903aee5adeff89c6d9a48c18d6 (diff) | |
| download | coreboot-01ebc74d5620f7cdbf3e51fae8e720e027d55f39.tar.gz coreboot-01ebc74d5620f7cdbf3e51fae8e720e027d55f39.tar.bz2 coreboot-01ebc74d5620f7cdbf3e51fae8e720e027d55f39.zip | |
soc/intel/common/block: Provide mmc.c for setting dll registers
Currently, we don't have UPDs to set emmc settings per mainboard on CML.
This code change is to create mmc.c to provide interface to override dll
settings per mainboard.
Notice: set_mmc_dll function will override the dll values in FSP.
BUG=b:131401116
BRANCH=none
TEST=Boot to OS and confirm the dll values have been overridden.
Change-Id: Ib3c72b9851f41585ec099d8ae83a721af87ed383
Signed-off-by: Kane Chen <kane.chen@intel.com>
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/common/block/include')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/mmc.h (renamed from src/soc/intel/common/block/include/intelblocks/early_mmc.h) | 31 |
2 files changed, 24 insertions, 9 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/chip.h b/src/soc/intel/common/block/include/intelblocks/chip.h index 9fe165e5b146..1e830d5d175d 100644 --- a/src/soc/intel/common/block/include/intelblocks/chip.h +++ b/src/soc/intel/common/block/include/intelblocks/chip.h @@ -18,6 +18,7 @@ #include <intelblocks/gspi.h> #include <drivers/i2c/designware/dw_i2c.h> +#include <intelblocks/mmc.h> enum { CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */ @@ -35,6 +36,7 @@ struct soc_intel_common_config { struct dw_i2c_bus_config i2c[CONFIG_SOC_INTEL_I2C_DEV_MAX]; /* PCH Thermal Trip Temperature in deg C */ uint8_t pch_thermal_trip; + struct mmc_dll_params emmc_dll; }; /* This function to retrieve soc config structure required by common code */ diff --git a/src/soc/intel/common/block/include/intelblocks/early_mmc.h b/src/soc/intel/common/block/include/intelblocks/mmc.h index 39aaf58fcf01..a8776ea84235 100644 --- a/src/soc/intel/common/block/include/intelblocks/early_mmc.h +++ b/src/soc/intel/common/block/include/intelblocks/mmc.h @@ -13,18 +13,12 @@ * GNU General Public License for more details. */ -#ifndef SOC_INTEL_COMMON_BLOCK_EARLY_MMC_H -#define SOC_INTEL_COMMON_BLOCK_EARLY_MMC_H +#ifndef SOC_INTEL_COMMON_BLOCK_MMC_H +#define SOC_INTEL_COMMON_BLOCK_MMC_H #include <stdint.h> /* - * Following should be defined in soc/iomap.h - * PRERAM_MMC_BASE_ADDRESS - Provide an address to setup emmc controller's - PCI BAR. - */ - -/* * Structure for the following delay registers * emmc_tx_data_cntl1: Tx Delay Control 1 (Tx_DATA_dly_1)-Offset 824h * emmc_tx_data_cntl2: Tx Delay Control 2 (Tx_DATA_dly_2)-Offset 828h @@ -60,9 +54,28 @@ int soc_configure_mmc_gpios(void); * returns 0, if able to get register settings; otherwise returns -1 */ int soc_get_mmc_dll(struct mmc_dll_params *params); +/* + * Set mmc delay register settings. + * bar: eMMC controller MMIO base address. + * returns 0, if able to set register settings; otherwise returns -1 + */ +int set_mmc_dll(void *bar); + +#define EMMC_TX_CMD_CNTL_OFFSET 0x820 +#define EMMC_TX_DATA_CNTL1_OFFSET 0x824 +#define EMMC_TX_DATA_CNTL2_OFFSET 0x828 +#define EMMC_RX_CMD_DATA_CNTL1_OFFSET 0x82C +#define EMMC_RX_STROBE_CNTL_OFFSET 0x830 +#define EMMC_RX_CMD_DATA_CNTL2_OFFSET 0x834 #if CONFIG(SOC_INTEL_COMMON_EARLY_MMC_WAKE) /* + * Following should be defined in soc/iomap.h + * PRERAM_MMC_BASE_ADDRESS - Provide an address to setup emmc controller's + PCI BAR. + */ + +/* * Initializes sdhci / mmc controller and sends CMD0, CMD1 to emmc card. * In case of success: It returns 0 and adds cbmem entry CBMEM_ID_MMC_STATUS * and sets it to 1. Payload can start by sending CMD1, there is no need to @@ -77,4 +90,4 @@ static inline int early_mmc_wake_hw(void) return -1; } #endif /* CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE */ -#endif /* SOC_INTEL_COMMON_BLOCK_EARLY_MMC_H */ +#endif /* SOC_INTEL_COMMON_BLOCK_MMC_H */ |