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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-03-01 16:53:22 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-06-29 21:51:20 +0000 |
| commit | c657ab9750dd040db2af9011d32c112bcdca8a5d (patch) | |
| tree | 7f38b159fad0bca57b5bf630f9561b295f2c5d04 /src/soc/intel/common/block/irq/Kconfig | |
| parent | b59980b54ebe22cc4dcbc0da63206c7f9ec47c28 (diff) | |
| download | coreboot-c657ab9750dd040db2af9011d32c112bcdca8a5d.tar.gz coreboot-c657ab9750dd040db2af9011d32c112bcdca8a5d.tar.bz2 coreboot-c657ab9750dd040db2af9011d32c112bcdca8a5d.zip | |
soc/intel/common/block/irq: Add support for intel_write_pci0_PRT
Add a new function to fill out the data structures necessary to generate
a _PRT table.
BUG=b:130217151, b:171580862, b:176858827
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I21a4835890ca03bff83ed0e8791441b3af54cb62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51159
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/irq/Kconfig')
| -rw-r--r-- | src/soc/intel/common/block/irq/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/irq/Kconfig b/src/soc/intel/common/block/irq/Kconfig index d4d9ab1b0372..ab6fc509cb12 100644 --- a/src/soc/intel/common/block/irq/Kconfig +++ b/src/soc/intel/common/block/irq/Kconfig @@ -1,6 +1,7 @@ config SOC_INTEL_COMMON_BLOCK_IRQ bool select SOC_INTEL_COMMON_BLOCK_GPIO + select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN help Intel common block support for assigning PCI IRQs dynamically. This allows coreboot to control the IRQ assignments. They are passed to the |