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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-29 09:57:05 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 16:36:26 +0000 |
| commit | 2ec1c13ac4a9724095ce71783fd52f70a0b1536d (patch) | |
| tree | df15407f69cfc7899aa06ad3f35dec32164c4d07 /src/soc/intel/common/block/p2sb/p2sb.c | |
| parent | b887adf7a56f2877c41e808002f30841a6679eb6 (diff) | |
| download | coreboot-2ec1c13ac4a9724095ce71783fd52f70a0b1536d.tar.gz coreboot-2ec1c13ac4a9724095ce71783fd52f70a0b1536d.tar.bz2 coreboot-2ec1c13ac4a9724095ce71783fd52f70a0b1536d.zip | |
soc/intel/common: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I09cc69a20dc67c0f48b35bfd2afeaba9e2ee5064
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/common/block/p2sb/p2sb.c')
| -rw-r--r-- | src/soc/intel/common/block/p2sb/p2sb.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 731ce50d4a3d..ff6c9dc26b49 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -23,7 +23,7 @@ void p2sb_enable_bar(void) pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0); /* Enable P2SB MSE */ - pci_write_config8(PCH_DEV_P2SB, PCI_COMMAND, + pci_write_config16(PCH_DEV_P2SB, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } |