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| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2020-02-12 16:01:22 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-25 10:13:36 +0000 |
| commit | 3f4af0da938e0d9f4d80e77a3d8abd1f6400e57e (patch) | |
| tree | f91f342cd93dbcf175016681b3fbdf887688886d /src/soc/intel/common/block/p2sb/p2sb.c | |
| parent | 7e8998466f6b0cfa410af94da41b18859d6379f2 (diff) | |
| download | coreboot-3f4af0da938e0d9f4d80e77a3d8abd1f6400e57e.tar.gz coreboot-3f4af0da938e0d9f4d80e77a3d8abd1f6400e57e.tar.bz2 coreboot-3f4af0da938e0d9f4d80e77a3d8abd1f6400e57e.zip | |
soc/intel/common: Update Jasper Lake Device IDs
Update Jasper Lake CPU, SA and PCH IDs.
BUG=b:149185282
BRANCH=None
TEST=Compilation for Jasper Lake board is working
Change-Id: I2c9ec1eb4236184b981d99250f263172c82f7117
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/soc/intel/common/block/p2sb/p2sb.c')
| -rw-r--r-- | src/soc/intel/common/block/p2sb/p2sb.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index c968409e0a07..5b72e72fe7b5 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -155,8 +155,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_P2SB, PCI_DEVICE_ID_INTEL_CMP_H_P2SB, PCI_DEVICE_ID_INTEL_TGL_P2SB, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_P2SB, PCI_DEVICE_ID_INTEL_EHL_P2SB, + PCI_DEVICE_ID_INTEL_JSP_P2SB, 0, }; |