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| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2019-10-21 22:25:04 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-05 15:05:22 +0000 |
| commit | 6b5bf407deb52a900ef0a8a0b99f853be1eb7e82 (patch) | |
| tree | 283c0d2d098d3439e1558729cbdb35f9721ab6e6 /src/soc/intel/common/block/p2sb/p2sb.c | |
| parent | 8fc523e3137cfdde970a3c87e22b8bbc586a3f7e (diff) | |
| download | coreboot-6b5bf407deb52a900ef0a8a0b99f853be1eb7e82.tar.gz coreboot-6b5bf407deb52a900ef0a8a0b99f853be1eb7e82.tar.bz2 coreboot-6b5bf407deb52a900ef0a8a0b99f853be1eb7e82.zip | |
soc/intel/common: Include Tigerlake device IDs
Add Tigerlake specific CPU, System Agent, PCH, IGD device IDs.
BUG=None
BRANCH=None
TEST=Build 'emerge-tglrvp coreboot'
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I19047354718bdf510dffee4659d885f1313a751b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/common/block/p2sb/p2sb.c')
| -rw-r--r-- | src/soc/intel/common/block/p2sb/p2sb.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 14e1fd90eb27..981ad078720b 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -179,6 +179,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNP_H_P2SB, PCI_DEVICE_ID_INTEL_ICL_P2SB, PCI_DEVICE_ID_INTEL_CMP_P2SB, + PCI_DEVICE_ID_INTEL_TGL_P2SB, 0, }; |