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| author | Subrata Banik <subrata.banik@intel.com> | 2017-12-07 14:55:51 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2017-12-13 10:20:32 +0000 |
| commit | 6bbc91a96468b97a3e19cdba4641d68e2f2a6f98 (patch) | |
| tree | f3f298b6aab6d1fc21cca733981aa609007639b4 /src/soc/intel/common/block/p2sb/p2sb.c | |
| parent | ffc790bc7fe35a992e81f0cc31433230a79dfb33 (diff) | |
| download | coreboot-6bbc91a96468b97a3e19cdba4641d68e2f2a6f98.tar.gz coreboot-6bbc91a96468b97a3e19cdba4641d68e2f2a6f98.tar.bz2 coreboot-6bbc91a96468b97a3e19cdba4641d68e2f2a6f98.zip | |
soc/intel/common/block: Add option to have subsystem_id in common pci driver
This patch ensures all Intel common PCI devices can
have subsystem ID programmed along with PCI resource
enabling (.enable_resources) as part of PCI enumeration
process.
TEST=Build and boot KBL/CNL/APL/GLK to ensure PCI
subsystem ID getting programmed.
Example:
Enabling resources...
PCI: 00:00.0 subsystem <- 8086/590c
PCI: 00:00.0 cmd <- 06
PCI: 00:02.0 subsystem <- 8086/591e
Change-Id: I46307b0db78c8864c85865bd0f3328d5141971be
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22768
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/p2sb/p2sb.c')
| -rw-r--r-- | src/soc/intel/common/block/p2sb/p2sb.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 63b9c8561360..6a9bd34668f8 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -64,6 +64,7 @@ static void read_resources(struct device *dev) static const struct device_operations device_ops = { .read_resources = read_resources, .set_resources = DEVICE_NOOP, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { |