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| author | John Zhao <john.zhao@intel.com> | 2022-03-09 17:19:33 -0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-21 14:16:07 +0000 |
| commit | b1dd019de2b7295315fd94ad89693980208f33fe (patch) | |
| tree | 7dee602109ab98269205a635f2669f40e5d1687f /src/soc/intel/common/block/p2sb/p2sb.c | |
| parent | 32d53c9df0a0c1889e43cdd7efff9c57c4f46f4e (diff) | |
| download | coreboot-b1dd019de2b7295315fd94ad89693980208f33fe.tar.gz coreboot-b1dd019de2b7295315fd94ad89693980208f33fe.tar.bz2 coreboot-b1dd019de2b7295315fd94ad89693980208f33fe.zip | |
soc/intel/common: Add IOE P2SB for TCSS
Meteor Lake has the IOE Die for TCSS. This change adds the IOE P2SB
sideband access and exposes API for TCSS usage.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Change-Id: I01f551b6e1f50ebdc1cef2ceee815a492030db19
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/common/block/p2sb/p2sb.c')
| -rw-r--r-- | src/soc/intel/common/block/p2sb/p2sb.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 1b0c080913db..2517f69e9689 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -139,8 +139,6 @@ static const struct device_operations device_ops = { static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_SOC_P2SB, - PCI_DID_INTEL_MTL_IOE_M_P2SB, - PCI_DID_INTEL_MTL_IOE_P_P2SB, PCI_DID_INTEL_APL_P2SB, PCI_DID_INTEL_GLK_P2SB, PCI_DID_INTEL_LWB_P2SB, |