soc/intel/cannonlake: Add new cannon lake PCH-H support

Cannon lake PCH-H is added to support coffee lake RVP11 and coffee lake
RVP8 platforms.

- Add new device IDs for LPC, PCIE, PMC, I2C, UART, SMBUS, XHCI, P2SB,
  SRAM, AUDIO, CSE0, XDCI, SD, MCH and graphics device.

- Add new device IDs to intel common code respectively.

- Add CPU, LPC, GD, MCH entry to report_platform.c to identify RVP11 & RVP8.

- CNL PCH-H supports 24 pcie root ports and 4 I2C controllers, hence chip.c
  is modified accordingly.

- Add board type UserBd UPD to BOARD_TYPE_DESKTOP for both RVP11 & RVP8.

BUG=None
TEST=successfully boot both CFL RVP11 & RVP8, verified all the enabled devices
     are enumerated and cross checked devices ids in serial logs and UEFI shell.

Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28718
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 1 insertions, 0 deletions

diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c
index c09c6aa7ef67..69e1f9780bb8 100644
--- a/src/soc/intel/common/block/p2sb/p2sb.c
+++ b/src/soc/intel/common/block/p2sb/p2sb.c
@@ -166,6 +166,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_APL_P2SB,
 	PCI_DEVICE_ID_INTEL_GLK_P2SB,
 	PCI_DEVICE_ID_INTEL_CNL_P2SB,
+	PCI_DEVICE_ID_INTEL_CNP_H_P2SB,
 	0,
 };