diff options
| author | Jeremy Soller <jackpot51@gmail.com> | 2023-05-17 14:52:03 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-23 20:21:39 +0000 |
| commit | 14d69d03b79958ca35ed39405570ff37cfebfe1f (patch) | |
| tree | 57c846ac65a2183aa43fbba80460fa0cdd5c1014 /src/soc/intel/common/block/pcie | |
| parent | f99d6700f167b70d883dd4ecf9a82bff21fea5d5 (diff) | |
| download | coreboot-14d69d03b79958ca35ed39405570ff37cfebfe1f.tar.gz coreboot-14d69d03b79958ca35ed39405570ff37cfebfe1f.tar.bz2 coreboot-14d69d03b79958ca35ed39405570ff37cfebfe1f.zip | |
soc/intel/common: Add RPP-S PCI IDs
Add PCI IDs to support Raptor Point PCH.
Ref: Intel 700 Series PCH Datasheet, Volume 1 (#743835, rev 2)
Change-Id: Iee410ed3179260b08d45f50e8126fb815c686324
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73437
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/pcie')
| -rw-r--r-- | src/soc/intel/common/block/pcie/pcie.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index d5d33225817d..d86ba831d15c 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -328,6 +328,34 @@ static const unsigned short pcie_device_ids[] = { PCI_DID_INTEL_ADP_M_N_PCIE_RP10, PCI_DID_INTEL_ADP_N_PCIE_RP11, PCI_DID_INTEL_ADP_N_PCIE_RP12, + PCI_DID_INTEL_RPP_S_PCIE_RP1, + PCI_DID_INTEL_RPP_S_PCIE_RP2, + PCI_DID_INTEL_RPP_S_PCIE_RP3, + PCI_DID_INTEL_RPP_S_PCIE_RP4, + PCI_DID_INTEL_RPP_S_PCIE_RP5, + PCI_DID_INTEL_RPP_S_PCIE_RP6, + PCI_DID_INTEL_RPP_S_PCIE_RP7, + PCI_DID_INTEL_RPP_S_PCIE_RP8, + PCI_DID_INTEL_RPP_S_PCIE_RP9, + PCI_DID_INTEL_RPP_S_PCIE_RP10, + PCI_DID_INTEL_RPP_S_PCIE_RP11, + PCI_DID_INTEL_RPP_S_PCIE_RP12, + PCI_DID_INTEL_RPP_S_PCIE_RP13, + PCI_DID_INTEL_RPP_S_PCIE_RP14, + PCI_DID_INTEL_RPP_S_PCIE_RP15, + PCI_DID_INTEL_RPP_S_PCIE_RP16, + PCI_DID_INTEL_RPP_S_PCIE_RP17, + PCI_DID_INTEL_RPP_S_PCIE_RP18, + PCI_DID_INTEL_RPP_S_PCIE_RP19, + PCI_DID_INTEL_RPP_S_PCIE_RP20, + PCI_DID_INTEL_RPP_S_PCIE_RP21, + PCI_DID_INTEL_RPP_S_PCIE_RP22, + PCI_DID_INTEL_RPP_S_PCIE_RP23, + PCI_DID_INTEL_RPP_S_PCIE_RP24, + PCI_DID_INTEL_RPP_S_PCIE_RP25, + PCI_DID_INTEL_RPP_S_PCIE_RP26, + PCI_DID_INTEL_RPP_S_PCIE_RP27, + PCI_DID_INTEL_RPP_S_PCIE_RP28, 0 }; |