soc/intel/skylake: Assign device ops in chipset devicetree

Some PCI IDs were missing, and at least one (SPT's fast SPI
device in a generic SPI driver) was wrong. Hence, this patch
actually changes behavior depending on the devices actually
present in a machine.

In this patch the Skylake devicetree is written in a single-line
style. Alternative, the device operations could be put on a separate
line, e.g.
    device pci 00.0 alias system_agent on
            ops systemagent_ops
    end

Tested on Kontron/bSL6. Notable in the log diff is that the
CSE and SATA drivers are hooked up now.

Change-Id: I8635fc53ca617b029d6fe1845eaef6c5c749db82
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

1 files changed, 2 insertions, 58 deletions

diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index d43528644cc0..d3fcbde38d70 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -56,7 +56,7 @@ static struct pci_operations pcie_ops = {
 	.set_subsystem = pci_dev_set_subsystem,
 };
 
-static struct device_operations device_ops = {
+struct device_operations pcie_rp_ops = {
 	.read_resources		= pci_bus_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources		= pci_bus_enable_resources,
@@ -81,38 +81,6 @@ static const unsigned short pcie_device_ids[] = {
 	PCI_DID_INTEL_MTL_IOE_P_PCIE_RP10,
 	PCI_DID_INTEL_MTL_IOE_P_PCIE_RP11,
 	PCI_DID_INTEL_MTL_IOE_P_PCIE_RP12,
-	PCI_DID_INTEL_SPT_LP_PCIE_RP1,
-	PCI_DID_INTEL_SPT_LP_PCIE_RP2,
-	PCI_DID_INTEL_SPT_LP_PCIE_RP3,
-	PCI_DID_INTEL_SPT_LP_PCIE_RP4,
-	PCI_DID_INTEL_SPT_LP_PCIE_RP5,
-	PCI_DID_INTEL_SPT_LP_PCIE_RP6,
-	PCI_DID_INTEL_SPT_LP_PCIE_RP7,
-	PCI_DID_INTEL_SPT_LP_PCIE_RP8,
-	PCI_DID_INTEL_SPT_LP_PCIE_RP9,
-	PCI_DID_INTEL_SPT_LP_PCIE_RP10,
-	PCI_DID_INTEL_SPT_LP_PCIE_RP11,
-	PCI_DID_INTEL_SPT_LP_PCIE_RP12,
-	PCI_DID_INTEL_SPT_H_PCIE_RP1,
-	PCI_DID_INTEL_SPT_H_PCIE_RP2,
-	PCI_DID_INTEL_SPT_H_PCIE_RP3,
-	PCI_DID_INTEL_SPT_H_PCIE_RP4,
-	PCI_DID_INTEL_SPT_H_PCIE_RP5,
-	PCI_DID_INTEL_SPT_H_PCIE_RP6,
-	PCI_DID_INTEL_SPT_H_PCIE_RP7,
-	PCI_DID_INTEL_SPT_H_PCIE_RP8,
-	PCI_DID_INTEL_SPT_H_PCIE_RP9,
-	PCI_DID_INTEL_SPT_H_PCIE_RP10,
-	PCI_DID_INTEL_SPT_H_PCIE_RP11,
-	PCI_DID_INTEL_SPT_H_PCIE_RP12,
-	PCI_DID_INTEL_SPT_H_PCIE_RP13,
-	PCI_DID_INTEL_SPT_H_PCIE_RP14,
-	PCI_DID_INTEL_SPT_H_PCIE_RP15,
-	PCI_DID_INTEL_SPT_H_PCIE_RP16,
-	PCI_DID_INTEL_SPT_H_PCIE_RP17,
-	PCI_DID_INTEL_SPT_H_PCIE_RP18,
-	PCI_DID_INTEL_SPT_H_PCIE_RP19,
-	PCI_DID_INTEL_SPT_H_PCIE_RP20,
 	PCI_DID_INTEL_LWB_PCIE_RP1,
 	PCI_DID_INTEL_LWB_PCIE_RP2,
 	PCI_DID_INTEL_LWB_PCIE_RP3,
@@ -153,30 +121,6 @@ static const unsigned short pcie_device_ids[] = {
 	PCI_DID_INTEL_LWB_PCIE_RP18_SUPER,
 	PCI_DID_INTEL_LWB_PCIE_RP19_SUPER,
 	PCI_DID_INTEL_LWB_PCIE_RP20_SUPER,
-	PCI_DID_INTEL_UPT_H_PCIE_RP1,
-	PCI_DID_INTEL_UPT_H_PCIE_RP2,
-	PCI_DID_INTEL_UPT_H_PCIE_RP3,
-	PCI_DID_INTEL_UPT_H_PCIE_RP4,
-	PCI_DID_INTEL_UPT_H_PCIE_RP5,
-	PCI_DID_INTEL_UPT_H_PCIE_RP6,
-	PCI_DID_INTEL_UPT_H_PCIE_RP7,
-	PCI_DID_INTEL_UPT_H_PCIE_RP8,
-	PCI_DID_INTEL_UPT_H_PCIE_RP9,
-	PCI_DID_INTEL_UPT_H_PCIE_RP10,
-	PCI_DID_INTEL_UPT_H_PCIE_RP11,
-	PCI_DID_INTEL_UPT_H_PCIE_RP12,
-	PCI_DID_INTEL_UPT_H_PCIE_RP13,
-	PCI_DID_INTEL_UPT_H_PCIE_RP14,
-	PCI_DID_INTEL_UPT_H_PCIE_RP15,
-	PCI_DID_INTEL_UPT_H_PCIE_RP16,
-	PCI_DID_INTEL_UPT_H_PCIE_RP17,
-	PCI_DID_INTEL_UPT_H_PCIE_RP18,
-	PCI_DID_INTEL_UPT_H_PCIE_RP19,
-	PCI_DID_INTEL_UPT_H_PCIE_RP20,
-	PCI_DID_INTEL_UPT_H_PCIE_RP21,
-	PCI_DID_INTEL_UPT_H_PCIE_RP22,
-	PCI_DID_INTEL_UPT_H_PCIE_RP23,
-	PCI_DID_INTEL_UPT_H_PCIE_RP24,
 	PCI_DID_INTEL_CNL_LP_PCIE_RP1,
 	PCI_DID_INTEL_CNL_LP_PCIE_RP2,
 	PCI_DID_INTEL_CNL_LP_PCIE_RP3,
@@ -387,7 +331,7 @@ static const unsigned short pcie_device_ids[] = {
 };
 
 static const struct pci_driver pch_pcie __pci_driver = {
-	.ops	= &device_ops,
+	.ops	= &pcie_rp_ops,
 	.vendor	= PCI_VID_INTEL,
 	.devices	= pcie_device_ids,
 };