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| author | Nico Huber <nico.h@gmx.de> | 2021-03-06 14:13:58 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-03-12 23:44:49 +0000 |
| commit | a768deae7346c5de740723331e3eb5ee04746bfe (patch) | |
| tree | d96270ac5f62f957f2848291676954d2611898b7 /src/soc/intel/common/block/pcie | |
| parent | 2d24146aef39ef5a6b1d061a81c8c9e333886b5c (diff) | |
| download | coreboot-a768deae7346c5de740723331e3eb5ee04746bfe.tar.gz coreboot-a768deae7346c5de740723331e3eb5ee04746bfe.tar.bz2 coreboot-a768deae7346c5de740723331e3eb5ee04746bfe.zip | |
device: Give `pci_ops.set_L1_ss_latency` a proper name
Rename `set_L1_ss_latency` to what it does: `set_ltr_max_latencies`.
TEST=Built google/brya0 with BUILD_TIMELESS=1: no changes.
Change-Id: I7008aa18bf80d6709dce1b2d3bfbb5ea407a0574
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51326
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/pcie')
| -rw-r--r-- | src/soc/intel/common/block/pcie/pcie.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 4f5687fd5f97..346c0ff22564 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -45,7 +45,7 @@ static void pch_pcie_init(struct device *dev) pci_write_config16(dev, PCI_SEC_STATUS, reg16); } -static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset) +static void pcie_set_ltr_max_latencies(struct device *dev, unsigned int offset) { /* Set max snoop and non-snoop latency for the SOC */ pci_write_config32(dev, offset, @@ -54,7 +54,7 @@ static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset) } static struct pci_operations pcie_ops = { - .set_L1_ss_latency = pcie_set_L1_ss_max_latency, + .set_ltr_max_latencies = pcie_set_ltr_max_latencies, .set_subsystem = pci_dev_set_subsystem, }; |