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| author | Jeff Daly <jeffd@silicom-usa.com> | 2022-01-10 23:47:35 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-17 14:52:41 +0000 |
| commit | e5ac30060298626cf12972209ea81a77d0569cde (patch) | |
| tree | eb34efb014f6f3afe6cefbcd831c060c5ce4a82f /src/soc/intel/common/block/spi | |
| parent | 24f7554e070ce11d902b7b78846158f802c4b952 (diff) | |
| download | coreboot-e5ac30060298626cf12972209ea81a77d0569cde.tar.gz coreboot-e5ac30060298626cf12972209ea81a77d0569cde.tar.bz2 coreboot-e5ac30060298626cf12972209ea81a77d0569cde.zip | |
soc/intel/denverton_ns: enable Denverton to use common SoC SPI code
Use Intel common SoC SPI code for Denverton refactor
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: Ic1d57c6b348adb934785b0e2bec4e856f0bf8d77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61014
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/spi')
| -rw-r--r-- | src/soc/intel/common/block/spi/spi.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 256e01a342f8..34607184d8a6 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -197,6 +197,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_ADP_M_N_SPI1, PCI_DID_INTEL_ADP_M_SPI2, PCI_DID_INTEL_SPR_HWSEQ_SPI, + PCI_DID_INTEL_DNV_SPI, 0 }; |