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| author | Sean Rhodes <sean@starlabs.systems> | 2024-01-10 20:38:05 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-05 14:09:05 +0000 |
| commit | 7201602a18b63fc5236f025d22dc726637866cb6 (patch) | |
| tree | 8372888b3a67a576d7a82e7f7ea3f1601817d37f /src/soc/intel/common/block/tcss/Kconfig | |
| parent | 4f43b0e7adb7f4699bae7b9a2f2fac2e797e9c4c (diff) | |
| download | coreboot-7201602a18b63fc5236f025d22dc726637866cb6.tar.gz coreboot-7201602a18b63fc5236f025d22dc726637866cb6.tar.bz2 coreboot-7201602a18b63fc5236f025d22dc726637866cb6.zip | |
soc/intel/common/tcss: Guard disabling MUX with TCSS_HAS_USBC_OPS
Currently, SOC_INTEL_COMMON_BLOCK_TCSS will set MUX to disabled. The two
related options to re-configure it for either USB devices or displays,
are currently only supported by the ChromeEC. As such, any device
without the ChromeEC will boot with attached USB-C devices in a
non-functional state.
Add TCSS_HAS_USBC_OPS to make this feature configurable, and set the
default to enabled if the board features the ChromeEC.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia848668ae9af4637fc7cffec9eb694f29d7deba9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79882
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/soc/intel/common/block/tcss/Kconfig')
| -rw-r--r-- | src/soc/intel/common/block/tcss/Kconfig | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/src/soc/intel/common/block/tcss/Kconfig b/src/soc/intel/common/block/tcss/Kconfig index 4af75fc559e0..7a8f52cc5481 100644 --- a/src/soc/intel/common/block/tcss/Kconfig +++ b/src/soc/intel/common/block/tcss/Kconfig @@ -2,17 +2,28 @@ config SOC_INTEL_COMMON_BLOCK_TCSS def_bool n select FSPS_USE_MULTI_PHASE_INIT help - Sets up USB2/3 port mapping in TCSS MUX and sets MUX to disconnect state + Sets up USB2/3 port mapping in TCSS MUX + +config TCSS_HAS_USBC_OPS + bool "Enable USB-C MUX operations via the EC" + default y if EC_GOOGLE_CHROMEEC + depends on SOC_INTEL_COMMON_BLOCK_TCSS + help + Enable USB-C operations via the EC. Requires `usbc_get_ops` to control features + such as HPD and DP Mode entry. Currently, only the ChromeEC implements this, see + (ec/google/chromeec/usbc_mux.c). + + This results in the MUX being set to a disabled state. config ENABLE_TCSS_DISPLAY_DETECTION bool "Enable detection of displays over USB Type-C ports with TCSS" - depends on SOC_INTEL_COMMON_BLOCK_TCSS && RUN_FSP_GOP + depends on TCSS_HAS_USBC_OPS && RUN_FSP_GOP help Enable displays to be detected over Type-C ports during boot. config ENABLE_TCSS_USB_DETECTION bool "Enable detection of USB boot devices attached to USB Type-C ports with TCSS" - depends on SOC_INTEL_COMMON_BLOCK_TCSS + depends on TCSS_HAS_USBC_OPS help Enable USB-C attached storage devices to be detected at boot. This option is required for some payloads (eg, edk2), without which devices attached |