diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-29 09:57:05 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 16:36:26 +0000 |
| commit | 2ec1c13ac4a9724095ce71783fd52f70a0b1536d (patch) | |
| tree | df15407f69cfc7899aa06ad3f35dec32164c4d07 /src/soc/intel/common/block/uart/uart.c | |
| parent | b887adf7a56f2877c41e808002f30841a6679eb6 (diff) | |
| download | coreboot-2ec1c13ac4a9724095ce71783fd52f70a0b1536d.tar.gz coreboot-2ec1c13ac4a9724095ce71783fd52f70a0b1536d.tar.bz2 coreboot-2ec1c13ac4a9724095ce71783fd52f70a0b1536d.zip | |
soc/intel/common: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I09cc69a20dc67c0f48b35bfd2afeaba9e2ee5064
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/common/block/uart/uart.c')
| -rw-r--r-- | src/soc/intel/common/block/uart/uart.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 7d75bdd62f27..9498060c5e11 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -68,7 +68,7 @@ void uart_common_init(const struct device *device, uintptr_t baseaddr) pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr); /* Enable memory access and bus master */ - pci_write_config32(dev, PCI_COMMAND, UART_PCI_ENABLE); + pci_write_config16(dev, PCI_COMMAND, UART_PCI_ENABLE); uart_lpss_init(device, baseaddr); } @@ -109,7 +109,7 @@ bool uart_is_controller_initialized(void) if (!base) return false; - if ((pci_read_config32(dev, PCI_COMMAND) & UART_PCI_ENABLE) + if ((pci_read_config16(dev, PCI_COMMAND) & UART_PCI_ENABLE) != UART_PCI_ENABLE) return false; |