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| author | Varshit Pandya <varshit.b.pandya@intel.com> | 2021-01-17 18:39:29 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-22 14:26:38 +0000 |
| commit | f4d98fdd20bbe3981684d32d3d3b257ab81163bb (patch) | |
| tree | 6d055b3f1cc54ab467e3deff6a1c43527fffdbc7 /src/soc/intel/common/block/uart/uart.c | |
| parent | f2d38baa983ad168466c5a5ac960da48ebaf34e2 (diff) | |
| download | coreboot-f4d98fdd20bbe3981684d32d3d3b257ab81163bb.tar.gz coreboot-f4d98fdd20bbe3981684d32d3d3b257ab81163bb.tar.bz2 coreboot-f4d98fdd20bbe3981684d32d3d3b257ab81163bb.zip | |
soc/intel/commmon: Include Alder Lake device IDs
Add Alder Lake M specific CPU, System AGent, PCH (Alder Point aka
ADP),
IGD device IDs.
Document Number: 619501, 626817
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: Ib13fe229f9e65eae8967aa20e28e29ac5c319265
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49629
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/uart/uart.c')
| -rw-r--r-- | src/soc/intel/common/block/uart/uart.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 3a64a16e6ff3..4a84935ad4a8 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -429,6 +429,10 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_ADP_P_UART4, PCI_DEVICE_ID_INTEL_ADP_P_UART5, PCI_DEVICE_ID_INTEL_ADP_P_UART6, + PCI_DEVICE_ID_INTEL_ADP_M_UART0, + PCI_DEVICE_ID_INTEL_ADP_M_UART1, + PCI_DEVICE_ID_INTEL_ADP_M_UART2, + PCI_DEVICE_ID_INTEL_ADP_M_UART3, 0, }; |