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| author | Tan, Lean Sheng <lean.sheng.tan@intel.com> | 2020-01-20 19:13:56 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-22 15:42:26 +0000 |
| commit | 26136092c01b8d29fde68058597b74923c21a41f (patch) | |
| tree | a95aa8cd3df3197a72d56e396dfa9fc86fb301fa /src/soc/intel/common/block/xhci/xhci.c | |
| parent | 8406179eff18144cad3584f28554186baf8e1a37 (diff) | |
| download | coreboot-26136092c01b8d29fde68058597b74923c21a41f.tar.gz coreboot-26136092c01b8d29fde68058597b74923c21a41f.tar.bz2 coreboot-26136092c01b8d29fde68058597b74923c21a41f.zip | |
soc/intel/common: Add Elkhartlake Device IDs
Add Elkhartlake CPU, SA and PCH IDs.
EHL PCH is code named as MCC.
Also add a MCH ID (JSL_EHL) which is shared by both JSL and EHL SKUs.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I03f15832143bcc3095a3936c65fbc30a95e7f0f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38489
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/xhci/xhci.c')
| -rw-r--r-- | src/soc/intel/common/block/xhci/xhci.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index e6a7e0db8584..4b8a5cc1ec2d 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -134,6 +134,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_H_XHCI, PCI_DEVICE_ID_INTEL_TGP_LP_XHCI, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_XHCI, + PCI_DEVICE_ID_INTEL_MCC_XHCI, 0 }; |