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| author | Subrata Banik <subrata.banik@intel.com> | 2018-05-28 16:12:03 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-06-07 21:58:19 +0000 |
| commit | 9cd99a1524cd8c7cd6100cfc9d68e85eea5ac265 (patch) | |
| tree | b5eaea43ae458551051d1f42d952603e60b98d49 /src/soc/intel/common/pch/lockdown/Kconfig | |
| parent | 6994bfefb59304140e6b65d4d71e0719b104d257 (diff) | |
| download | coreboot-9cd99a1524cd8c7cd6100cfc9d68e85eea5ac265.tar.gz coreboot-9cd99a1524cd8c7cd6100cfc9d68e85eea5ac265.tar.bz2 coreboot-9cd99a1524cd8c7cd6100cfc9d68e85eea5ac265.zip | |
soc/intel/common/pch: Add pch lockdown code
pch lockdown functionality can be used by supported PCH.
Right now pch lockdown functionality is applied for SPT
(Skylake SOC) and CNP(Cannon Lake SOC) PCH.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL and CNL platform.
Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/common/pch/lockdown/Kconfig')
| -rw-r--r-- | src/soc/intel/common/pch/lockdown/Kconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/common/pch/lockdown/Kconfig b/src/soc/intel/common/pch/lockdown/Kconfig new file mode 100644 index 000000000000..8fce5e785c23 --- /dev/null +++ b/src/soc/intel/common/pch/lockdown/Kconfig @@ -0,0 +1,7 @@ +config SOC_INTEL_COMMON_PCH_LOCKDOWN + bool + default n + help + This option allows to have chipset lockdown for DMI, FAST_SPI and + soc_lockdown_config() to implement any additional lockdown as PMC, + LPC for supported PCH. |