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| author | Angel Pons <th3fanbus@gmail.com> | 2021-02-19 20:01:31 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-03-01 19:39:05 +0000 |
| commit | 19af7bc822ada5a60ffbbd5fe233434cbbf9ae09 (patch) | |
| tree | e6a2d9f82cb98fa6435f2fd21f20c3e41bd6d4dd /src/soc/intel/common/pch | |
| parent | 8a269deee6617d488b1cd4a9c51af0949cb79eca (diff) | |
| download | coreboot-19af7bc822ada5a60ffbbd5fe233434cbbf9ae09.tar.gz coreboot-19af7bc822ada5a60ffbbd5fe233434cbbf9ae09.tar.bz2 coreboot-19af7bc822ada5a60ffbbd5fe233434cbbf9ae09.zip | |
soc/intel/skylake: Correct SMBUS_SLAVE_ADDR definition
According to document 332691-003EN (SPT-H datasheet volume 2), the
hardware defaults to 0x44, which matches what newer platforms use.
Change-Id: I494587b0074ab3675c3e88676375f667e757cdf0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50941
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/pch')
0 files changed, 0 insertions, 0 deletions