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| author | Sean Rhodes <sean@starlabs.systems> | 2022-06-20 08:09:29 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-22 18:34:33 +0000 |
| commit | 026f00476e11f6e9e53d19fba09d4d97c54e79cf (patch) | |
| tree | b66d8f4c4a76afec9e35dbc199b918d72588e6db /src/soc/intel/common | |
| parent | 80503e3c54b34c5ceed5edf2d4f2454e57a10c33 (diff) | |
| download | coreboot-026f00476e11f6e9e53d19fba09d4d97c54e79cf.tar.gz coreboot-026f00476e11f6e9e53d19fba09d4d97c54e79cf.tar.bz2 coreboot-026f00476e11f6e9e53d19fba09d4d97c54e79cf.zip | |
soc/intel/common/pch: Add a block specific to Apollo Lake
Add SOC_INTEL_COMMON_PCH_CLIENT which is specific to Apollo
Lake. This is used to select the options that Apollo Lake
requires, without the ones specific to a PCH as Apollo Lake
doesn't have a PCH.
This change also enables SOC_INTEL_COMMON_PCH_LOCKDOWN for
Apollo Lake.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I084a05f904a19f3b7e9a071636659670aa45bf3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/pch/Kconfig | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index f46b95dec902..4934bb089641 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -1,3 +1,11 @@ +config SOC_INTEL_INTEGRATED_SOUTHCLUSTER + bool + help + Apollo Lake and Gemini Lake are single-chip platforms with a south + cluster instead of a PCH. Most of the IP blocks are the same as in + PCH platforms, but there are several differences that need to be + accounted for. + config SOC_INTEL_COMMON_PCH_CLIENT bool select SOC_INTEL_COMMON_PCH_BASE @@ -33,24 +41,27 @@ config PCH_SPECIFIC_BASE_OPTIONS select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG - select SOC_INTEL_COMMON_BLOCK_GPMR select SOC_INTEL_COMMON_BLOCK_ITSS select SOC_INTEL_COMMON_BLOCK_LPC - select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR select SOC_INTEL_COMMON_BLOCK_P2SB select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_PMC select SOC_INTEL_COMMON_BLOCK_RTC - select SOC_INTEL_COMMON_BLOCK_SATA select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_TCO - select SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_PCH_LOCKDOWN select SOUTHBRIDGE_INTEL_COMMON_SMBUS +config PCH_SPECIFIC_DISCRETE_OPTIONS + def_bool !SOC_INTEL_INTEGRATED_SOUTHCLUSTER + select SOC_INTEL_COMMON_BLOCK_GPMR + select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR + select SOC_INTEL_COMMON_BLOCK_SATA + select SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS + config PCH_SPECIFIC_CLIENT_OPTIONS def_bool SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_BLOCK_DSP |